SFFSAO5 April 2026 TXE8116-Q1
4.1 VSSOP Package
This section provides a failure mode analysis (FMA) for the pins of the TXE8116-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to VCC (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Table 4-1 shows the TXE8116-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TXE8116-Q1 datasheet.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| INT | 1 | The interrupt function is stuck low, and functionality of the pin is lost. | B |
| SDO | 2 | The push-pull SDO pin is stuck in a logic-low state. Damage to the p-channel FET potentially occurs due to high current draw when driving logic-high during communication. | A |
| VCC | 3 | The device is held in reset and all functionality is lost. All Px.y pins become Hi-Z. | B |
| GND | 4 | There is no effect on the device. This is the intended connection for this pin. | D |
| P0.0 –
P0.7 P1.0 – P1.7 | 5 – 20 | If the pin is configured to be an output high, damage to the p-channel FET potentially occurs due to high current draw. | A |
| If the pin is configured as an input or output low, the functionality of the pin is lost. | B | ||
| CS | 21 | Chip select is always in an active state and SPI communication is not possible. | B |
| SCLK | 22 | The communication clock is stuck in a logic-low state, which disables the data shift register from the SDI pin, and does not allow SDO data to be available to the controller. | B |
| SDI | 23 | The SDI pin is stuck in a logic-low state, which does not allow for any data from the controller to be sent through the SPI to the device. | B |
| RESET/FAIL-SAFE | 24 | The device is held in reset, functionality is lost, and the Px.y pins remain Hi-Z inputs. | B |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| INT | 1 | The INT pin can no longer assert low, controller cannot be notified of interrupts. | B |
| SDO | 2 | The device cannot send SPI data to the SPI controller, and functionality is lost. | B |
| VCC | 3 | The functionality of the pin is lost. | B |
| GND | 4 | The device is not biased to GND. There is damage to device if GND floats excessively high or low. | A |
| P0.0 –
P0.7 P1.0 – P1.7 | 5 – 20 | If the pin is configured to be an input, higher in-rush supply current potentially triggers INT due to a floating input. | B |
| If the pin is configured as an output, there is no damage to the device. | D | ||
| CS | 21 | A floating CS pin potentially makes SPI communication indeterminate, and functionality of the pin is lost. | B |
| SCLK | 22 | A floating SCLK pin potentially makes SPI communicate indeterminate, and disables the data shift register from the SDI pin, and does not allow SDO data to be available to the controller. | B |
| SDI | 23 | A floating SDI pin potentially causes wrong data to be latched, and the functionalities of the pin is lost. | B |
| RESET/FAIL-SAFE | 24 | A floating RESET pin potentially makes the device unresponsive or affects the programmed pin functions if the pin floats to logic-low. | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| INT | 1 | SDO | The SDO pin toggles the INT pin, causing false interrupts to trigger. | B |
| SDO | 2 | VCC | The push-pull SDO pin is stuck in a logic-low state. Damage to the p-channel FET potentially occurs due to high current draw when driving logic-high during communication. | A |
| VCC | 3 | GND | The device is not powered and all functionality is lost. | B |
| GND | 4 | P0.0 | If the pin is configured as an input or output low, the functionality of the pin is lost. | B |
| If the pin is configured to be an output high, damage to the p-channel FET potentially occurs due to high current draw. | A | |||
| P0.0 | 5 | P0.1 | If pins P0.0 and P0.1 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.0 and P0.1 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.0 and P0.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.0 and P0.1 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P0.1 | 6 | P0.2 | If pins P0.1 and P0.2 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.1 and P0.2 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.1 and P0.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.1 and P0.2 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P0.2 | 7 | P0.3 | If pins P0.2 and P0.3 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.2 and P0.3 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.2 and P0.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.2 and P0.3 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P0.3 | 8 | P0.4 | If pins P0.3 and P0.4 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.3 and P0.4 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.3 and P0.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.3 and P0.4 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P0.4 | 9 | P0.5 | If pins P0.4 and P0.5 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.4 and P0.5 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.4 and P0.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.4 and P0.5 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P0.5 | 10 | P0.6 | If pins P0.5 and P0.6 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.5 and P0.6 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.5 and P0.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.5 and P0.6 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P0.6 | 11 | P0.7 | If pins P0.6 and P0.7 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P0.6 and P0.7 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P0.6 and P0.7 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P0.6 and P0.7 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.7 | 13 | P1.6 | If pins P1.7 and P1.6 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.7 and P1.6 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.7 and P1.6 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.7 and P1.6 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.6 | 14 | P1.5 | If pins P1.6 and P1.5 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.6 and P1.5 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.6 and P1.5 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.6 and P1.5 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.5 | 15 | P1.4 | If pins P1.5 and P1.4 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.5 and P1.4 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.5 and P1.4 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.5 and P1.4 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.4 | 16 | P1.3 | If pins P1.4 and P1.3 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.4 and P1.3 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.4 and P1.3 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.4 and P1.3 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.3 | 17 | P1.2 | If pins P1.3 and P1.2 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.3 and P1.2 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.3 and P1.2 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.3 and P1.2 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.2 | 18 | P1.1 | If pins P1.2 and P1.1 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.2 and P1.1 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.2 and P1.1 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.2 and P1.1 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.1 | 19 | P1.0 | If pins P1.1 and P1.0 are configured as outputs with opposite logic levels, then contention between the pins occurs. If the IOH specification is exceeded then damage to the device potentially occurs. | A |
| If pins P1.1 and P1.0 are configured as outputs with same logic level, then damage to the device does not occur. | D | |||
| If pins P1.1 and P1.0 are configured so that one pin is an output and the other pin is an input, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| If pins P1.1 and P1.0 are configured as inputs, then no damage to the device is expected, but potentially leads to false interrupts. | C | |||
| P1.0 | 20 | CS | If pin P1.0 is an input, false interrupts potentially occur when the CS pin toggles. | C |
| If pin P1.0 is as output, the CS pin is potentially unusable and functionality of the pin is lost. | B | |||
| CS | 21 | SCLK | The CS pin toggles with the SCLK pin, SPI communication is not usable, and functionality of the pin is lost. | B |
| SCLK | 22 | SDI | SPI communication to the device is incorrect and functionality of the pin is lost. | B |
| SDI | 23 | RESET/FAIL-SAFE | The device is reset when the SDI pin is logic low, and functionality of the pin is lost. | B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to VCC
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| INT | 1 | If the INT pin is asserted low, damage to the n-channel FET potentially occurs due to high current sink. | A |
| SDO | 2 | The push-pull SDO pin is stuck in a logic-high state, damage to the n-channel FET potentially occurs due to high current sink when driving logic-high during communication. | A |
| VCC | 3 | There is no effect on the device. This is the intended use of this pin. | D |
| GND | 4 | The device is not powered and all functionality is lost. | B |
| P0.0 –
P0.7 P1.0 – P1.7 | 5 – 20 | If the pin is configured as an input or output high, the functionality of the pin is lost. | B |
| If the pin is configured to be an output low, damage to the n-channel FET potentially occurs due to high current sink. | A | ||
| CS | 21 | The chip select pin is stuck in the logic-high state, and SPI communication is not possible. | B |
| SCLK | 22 | The communication clock is stuck in a logic-high state, and disables the data shift register from the SDI pin, and does not allowing SDO data to be available to the controller. | B |
| SDI | 23 | The SDI pin is stuck in a logic-high state and does not allow for any data from the controller to be sent through the SPI to the device. | B |
| RESET / FAIL-SAFE | 24 | If RESET is tied to a pullup voltage, then higher leakage currents potentially occur. | C |
| If RESET is tied to a pullup voltage, and an external circuit attempts to drive RESET, the device is not able to be reset through this hardware pin. | B |