SFFS141 December   2021 TCAN1167-Q1

 

  1.   1
    1.     2
  2.   3
  3.   4
    1.     5
  4.   6
    1.     7
    2.     8
    3.     9
    4.     10
    5.     11
    6.     12
    7.     13
  5.   14
    1.     15
    2.     16
    3.     17
      1.      18
        1.       19
        2.       20
        3.       21
        4.       22
        5.       23
      2.      24
        1.       25
        2.       26
        3.       27
        4.       28
      3.      29
        1.       30
        2.       31
        3.       32
        4.       33
      4.      34
        1.       35
      5.      36
        1.       37
        2.       38
        3.       39
        4.       40
    4.     41
      1.      42
      2.      43
      3.      44
  6.   45
  7.   46
    1.     47
    2.     48
    3.     49
  8.   50

Fault Reporting

The TCAN1167-Q1 utilizes interrupt registers for fault reporting. The global register is provided from the device whenever nCS is pulled low and a valid clock is provided on the SCLK pin. This register provides information on where to find other interrupts.
Table 5-1 INT_GLOBAL Register Field Descriptions (Address = 50h)
Bit Field Type Reset Description
7 GLOBALERR RH 0b Logical OR of all interrupts
6 INT_1 RH 0b Logical OR of INT_1 register
5 INT_2 RH 0b Logical OR of INT_2 register
4 INT_3 RH 0b Logical OR of INT_3 register
3 INT_CANBUS RH 0b Logical OR of INT_CANBUS register
2-0 RSVD R 0b Reserved
Table 5-2 INT_1 Register Field Descriptions (Address = 51h)
Bit Field Type Reset Description
7 WD R/W1C 0b Watchdog event interrupt.
NOTE: This interrupt bit will be set for every watchdog error event and does not reliy upon the Watchdog error counter
6 CANINT R/W1C 0b CAN bus wake up interrupt
5 LWU R/W1C 0b Local wake up
4 WKERR R/W1C 0b Wake error bit is set when the SWE timer has expired and the state machine has returned to Sleep mode
3 RSVD R 0b Reserved
2 CANSLNT R/W1C 0b CAN silent
1 RSVD R 0b Reserved
0 CANDOM R/W1C 0b CAN bus stuck dominant
Table 5-3 INT_2 Register Field Descriptions (Address = 52h)
Bit Field Type Reset Description
7 RSVD R 0b Reserved
6 PWRON R/W1C 1b Power on
5 OVCCOUT R/W1C 0b VCCOUT overvoltage
4 UVSUP R/W1C 0b VSUP undervoltage
3 RSVD R 0b Reserved
2 UVCCOUT R/W1C 0b VCCOUT undervoltage
1 TSD R/W1C 0b Thermal Shutdown
0 TSDW R/W1C 0b Thermal Shutdown Warning
Table 5-4 INT_3 Register Field Descriptions (Address = 53h)
Bit Field Type Reset Description
7 SPIERR R/W1C 0b Sets when SPI status bit sets
6-0 RSVD R 00h Reserved
Table 5-5 INT_CANBUS Register Field Descriptions (Address = 54h)
Bit Field Type Reset Description
7:6 RESERVED R 0b Reserved. Reads return 0.
5 CANHCANL R/W1C 0b CANH and CANL shorted together
4 CANHBAT R/W1C 0b CANH shorted to Vbat
3 CANLGND R/W1C 0b CANL shorted to GND
2 CANBUSOPEN R/W1C 0b CAN bus open
1 CANBUSGND R/W1C 0b CAN bus shorted to GND or CANH shorted to GND
0 CANBUSBAT R/W1C 0b CAN bus shorted to Vbat or CANL shorted to Vbat