SFFS141 December   2021 TCAN1167-Q1

 

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TCAN1167-Q1 Component Overview

The TCAN1167-Q1 is a high speed Controller Area Network (CAN) system basis chip (SBC) that meets the physical layer requirements of the ISO 11898-2:2016 high speed CAN specification. The transceiver supports both classical CAN and CAN FD networks up to 8 megabits per second (Mbps).

The TCAN1167-Q1 supports a wide input supply range and integrates a 5-V LDO output. The 5-V LDO output (VCCOUT) supplies the CAN transceiver voltage internally as well as additional current externally.

The TCAN1167-Q1 allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that may be present on a system via the INH output pin. This allows an ultra-low-current sleep state where power is gated to all system components except for the TCAN1167-Q1, while monitoring the CAN bus. When a wake-up event is detected, the TCAN1167-Q1 initiates system start-up by driving INH high.

GUID-20210217-CA0I-9T61-FBTZ-4HTZZQPRTBMR-low.gif Figure 5-1 TCAN1167-Q1 Block Diagram
Figure 5-2 Potential Failure Points
Table 5-7 Potential Failure Points and Safety Mechanisms
Potential Failure Point Potential Failure Point Description Section
1 CAN communication See Section 5.3.1.1, Section 5.3.1.2, Section 5.3.1.3, Section 5.3.2.1
2 Supply voltage rail monitoring See Section 5.3.2.1, Section 5.3.2.2, Section 5.3.2.3, Section 5.3.2.4
3 SPI/Processor communication See Section 5.3.1.4, Section 5.3.3.1, Section 5.3.3.2, Section 5.3.3.3, Section 5.3.3.4, Section 5.3.4.1
4 EEPROM See Section 5.3.4.1
5 Floating pins See Section 5.3.5.1, Section 5.3.5.2, Section 5.3.5.3, Section 5.3.5.4