SFFS028A June 2022 – November 2025 TMP112-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TMP112-Q1 and TMP112D-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-6 and Table 4-6)
Pin open-circuited (see Table 4-7 and Table 4-7)
Pin short-circuited to an adjacent pin (see Table 4-8 and Table 4-8)
Pin short-circuited to supply (see Table 4-9 and Table 4-9)

Table 4-6 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality.
B	No device damage, but loss of functionality.
C	No device damage, but performance degradation.
D	No device damage, no impact to functionality or performance.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

The device is the only target on the I2C bus.
There is an external pullup resistor on the SCL and SDA pins.