SDAA393 June   2026 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Functional Safety Fundamentals
    1. 1.1 What is Functional Safety
    2. 1.2 Causality Chain from Fault to Harm
    3. 1.3 Core Problems Addressed by Functional Safety
  5. 2Safety Standards and Grade Classification
    1. 2.1 Major Safety Standard Systems
    2. 2.2 Functional Safety in Industrial Communication (FSoE)
    3. 2.3 Safety Grade Indicator System
      1. 2.3.1 IEC 61508 - Safety Integrity Level (SIL)
      2. 2.3.2 ISO 13849-1 - Performance Level (PL) and Category (CAT)
  6. 3System Safety Goal Decomposition
    1. 3.1 HARA Process and Safety Goal Definition
    2. 3.2 Safety Goal Decomposition and ASIL/SIL Assignment
    3. 3.3 Concrete Application of System-Level Decomposition
    4. 3.4 Role and Responsibility Division
  7. 4TI Chip Safety Architecture
    1. 4.1 MCU-Level Safety Architecture
    2. 4.2 Integrated Safety Mechanisms/Technology in TI MCU/MPU
      1. 4.2.1 Freedom From Interference (FFI) Design
      2. 4.2.2 Memory Protection and ECC Technology
      3. 4.2.3 Other Integrated Safety Mechanisms
  8. 5Functional Safety PLC Architecture Design
    1. 5.1 Necessity and Application Scenarios of Functional Safety PLC
    2. 5.2 Functional Safety PLC Architecture Design
    3. 5.3 Design Implementation Cases
    4. 5.4 TI Functional Safety Design Resources
  9. 6Summary
  10. 7References

5.2 Functional Safety PLC Architecture Design

Functional safety PLC key concepts are layering, isolation, and redundancy.

Separate Safety MCU with Standard MCU System Concept Figure 5-1 Separate Safety MCU with Standard MCU System Concept

Control Processor (Central Processor)

  • High-performance MPU (e.g., AM64x or AM243x)
  • Run PLC scan cycles and user logic
  • Handle multiple industrial communication protocols

Safety Subsystem (Safety Subsystem)

  • Two independent safety MCUs (AM243x or C2000)
  • Separate SRAM, ROM and peripherals for each
  • Cross-check via SPI interface
  • Output: Fault diagnosis, status reporting
  • Isolated relay driver or direct GPIO control

Comm Redundancy Management (DLR / Ring Network)

  • AM243x/AM64x built-in DLR supervisor manager
  • Maintain two independent communication paths
  • PRU_ICSSG performs fast fault detection and transfer
  • Ethernet switch-based redundancy
  • Handled at industrial Ethernet link layer

I/O Modules

  • Modular design
  • Support various I/O types (DI/DO/AI/AO)
  • Optional fault detection (high-end modules)