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  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Data Converter Architecture Overview
      1. 2.1.1 String DAC
      2. 2.1.2 R-2R DAC
      3. 2.1.3 Multiplying DAC
    2. 2.2 Data Converter Parameters
      1. 2.2.1 Resolution
      2. 2.2.2 Reference Type
      3. 2.2.3 Number of Channels
      4. 2.2.4 Interface Types
      5. 2.2.5 Output Types
      6. 2.2.6 Integral Nonlinearity and Differential Nonlinearity
      7. 2.2.7 Settling Time and Update Time
      8. 2.2.8 Physical Properties
      9. 2.2.9 Notable Features
  6. 3Summary
    1. 3.1 Example Devices
    2. 3.2 Other Resources
  7. 4References

2.1.1 String DAC

The string DAC consists of 2N resistors in series, where N is the resolution of the DAC. The resistors are connected between the positive DAC reference voltage (VREF) and the negative DAC reference voltage. This architecture provides a constant input impedance for the reference voltage and a structure best suited for low-cost, low-power designs. The code latched by the DAC closes the corresponding switch and divides the reference voltage to the desired output level before connecting directly to the output buffer. This output buffer provides low output impedance for driving loads and isolates the reference voltage source from external loading conditions.

String DACs become inefficient at greater resolutions as the number of resistors in the design increases. Each input code represents a resistor and switch, so the increase in resistors is exponential. An 8-bit string DAC only requires 256 resistors, but a 16-bit string DAC requires 65536 resistors. This architecture is inherently monotonic which means a positive code step never produces a negative change in output voltage and vice versa. Since a single code change only involves two active switches, strings DACs have low glitch energy. Figure 2-1 shows a simple diagram of the string DAC architecture.

String DAC Architecture Figure 2-1 String DAC Architecture