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  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Data Converter Architecture Overview
      1. 2.1.1 String DAC
      2. 2.1.2 R-2R DAC
      3. 2.1.3 Multiplying DAC
    2. 2.2 Data Converter Parameters
      1. 2.2.1 Resolution
      2. 2.2.2 Reference Type
      3. 2.2.3 Number of Channels
      4. 2.2.4 Interface Types
      5. 2.2.5 Output Types
      6. 2.2.6 Integral Nonlinearity and Differential Nonlinearity
      7. 2.2.7 Settling Time and Update Time
      8. 2.2.8 Physical Properties
      9. 2.2.9 Notable Features
  6. 3Summary
    1. 3.1 Example Devices
    2. 3.2 Other Resources
  7. 4References

2.1.2 R-2R DAC

The R-2R DAC (or back-DAC) architecture uses two resistor values of R and 2R to form a repeating pattern, with each 2R component of the design connected to either VREF or GND by a switch. The state of each switch depends on the latched input code to the DAC. The MSB controls the switch closest to VOUT and LSB controls the switch farthest from VOUT. The reference voltage input impedance of the R-2R architecture changes according to the digital input code. The R-2R design is commonly used for higher resolution devices, as they only require 2N resistors, where N is the resolution of the DAC. R-2R DACs provide high resolutions up to 16 or 20 bits and better noise performance. This type of DAC is not inherently monotonic.

Figure 2-2 shows a diagram of the R-2R DAC architecture.

R-2R DAC Architecture Figure 2-2 R-2R DAC Architecture

R-2R DACs have higher glitch energy as more switches are changed at once depending on the code-to-code transition. A 4-bit DAC changing its input code from 1000'b to 0111'b involves all four switches changing their state, otherwise known as a major carry transition. This type of midscale code change often produces the highest glitch energy.

Figure 2-3 shows an example of a major carry transition. At step 1 in the graph, the output voltage is settling from the previous code change. At step 2, there is a rise in the output voltage due to the major carry transition. At step 3, there is a larger voltage drop as the switches settle.

Major Carry Transition Glitch Voltage Figure 2-3 Major Carry Transition Glitch Voltage