SDAA286 March   2026 MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Idle-Low State: PWM Output Channel Low-state Configuration
  6. 3 Asymmetric PWM: Dual Synchronized PWM Generation with Phase Shift Control
    1. 3.1 Using Phase Load Functionality
      1. 3.1.1 Configuration for the Primary Timer (Main Timer)
      2. 3.1.2 Configuration for the Secondary Timer
      3. 3.1.3 Implementation for Cross Trigger Function
    2. 3.2 Using Secondary Capture-Compare Channels
  7. 4 Bit-Banging Emulation: Software-based Communication Protocol Implementation
    1. 4.1 Emulation of UART Rx Using TIMA
    2. 4.2 Emulation of UART Tx Using TIMA
  8. 5 Feedback-Based PWM Generation
    1. 5.1 Feedback-Based PWM Signal Replication
    2. 5.2 Delayed PWM Signal Generation Using an Input Reference
  9. 6 Delayed Timer Start: Synchronized Timer Instances Initiation with Configurable Delays
  10. 7 Stopping a Running Timer Based on Hardware Events
  11. 8 Dynamic PWM Update: Duty Cycle and Time Period Adjustment
    1. 8.1 Shadow Load and Shadow Compare Features
    2. 8.2 Arbitrary Signal Generation with DMA
  12. 9 Summary
  13. 10References

3.2 Using Secondary Capture-Compare Channels

TIMA0 with its 4 external and 2 internal CC channels can be independently used to generate 3 phase shifted PWMs. This can be achieved by utilizing the internal CC channels' SECONDARY CC event. GPTIMER provides the feature of choosing the secondary CC channel by configuring the CCCTL.CC2SELD or CCCTL.CC2SELU, depending on the counting mode(down, up, up-down).

Diagrammatic Representation of Asymmetric PWM generation using TIMA0 with Secondary Channel ApproachFigure 3-2 Diagrammatic Representation of Asymmetric PWM generation using TIMA0 with Secondary Channel Approach

Based on the secondary channel selected, output generation can be done by configuring the CCACT.CC2UACT or CCACT.CC2DACT depending on the counting mode(down, up, up-down).

For example, if counter Load value is 10000 and counter is in down counting mode and CC4 value is 9000.

CCCTL[1].CC2SELD is configured as 0x4 meaning CC4 is chosen as the secondary CC channel for the main channel CC1.

CCACT[1].CC2DACT is configured as 0x1 meaning CC output value would be set as HIGH whenever counter reaches 9000 in value, which is the current CC4 value. CC4 will act as the pseudo load value for CC1.

It would be observed that the output of CC1 would go HIGH every time the counter reaches 9000 because of the CCACT[1].CC2DACT. PWM output will go LOW when the counter reaches 4000 (CC1 value).

Implementing this approach to generate three phase shifted PWMs can be useful. Using cross-trigger function to generate more sync shifted PWM output channels with multiple Timer instances.

Following the configuration sequence below to set the secondary CC channel:

  • In the TIMA.CTRCTL, set the desired counter control settings for:
    • Counting Mode(CM) and Count Value After Enable(CVAE).
    • CLC, CZC, CAC to specify what condition controls zeroing, advancing or loading the counter
  • Set the TIMA.LOAD value to configure the PWM period
  • Set TIMA.CCCTL_xy[0/1].COC=0 for Compare Mode
  • Configure CCP as an output for the CC block by setting respective bit in the CCPD registers.
  • In TIMA.OCTL_xy[0/1], set CCPO = 0 to select the signal generator output.
  • Enable the corresponding CCP output by setting ODIS.C0CCPn to 0 for the corresponding counter n.
  • Configure polarity of the signal using the CCPOINV bit and configure CCPIV to specify the CCP output state while counter is disabled.
  • Configure CCCTL.CC2SELD field for CC0, as 3 meaning CC3 is used as the secondary CC block.
  • Configure CCCTL.CC2SELD field for CC1, as 4 meaning CC4 is used as the secondary CC block.
  • Configure CCCTL.CC2SELD field for CC2, as 5 meaning CC5 is used as the secondary CC block.
  • Configure CC3 depending on the phase shift required for example, if the phase shift is needed for 500 TIMCLK cycles configure CC3= Load value – 500=9500.
  • Configure CC4 depending on the phase shift required for example, if the phase shift is needed for 1000 TIMCLK cycles configure CC4= Load value – 1000=9000.
  • Configure CC5 depending on the phase shift required for example, if the phase shift is needed for 2000 TIMCLK cycles configure CC5= Load value – 2000=8000.
  • Configure CC0, CC1, CC2 based on the required duty cycle with CC3, CC4 and CC5 as the reference respectively.
  • CC3, CC4 and CC5 values will act as the pseudo load values for CC0, CC1 and CC2 respectively.
  • Configure CCACT.CC2DACT for CC0, CC1 and CC2 as 0x1 to set the output high whenever counter reaches the CC3, CC4 and CC5 values respectively.
  • Configure CCACT.CDACT for CC0, CC1 and CC2 as 0x2 to clear the output low whenever counter reaches the CC0, CC1 and CC2 values respectively.
  • Enable the counter by setting TIMA.CTRCTL.EN = 1.
/* TIMA0 Configuration for Generating Phase Shifted PWMs Using Secondary CC events */
static const DL_TimerA_ClockConfig gPWM_0ClockConfig = {
    .clockSel = DL_TIMER_CLOCK_BUSCLK,
    .divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
    .prescale = 255U
};

static const DL_TimerA_PWMConfig gPWM_0Config = {
    .pwmMode = DL_TIMER_PWM_MODE_EDGE_ALIGN,
    .period = 10000,
    .isTimerWithFourCC = true,
    .startTimer = DL_TIMER_STOP,
};

SYSCONFIG_WEAK void SYSCFG_DL_PWM_0_init(void) {

    DL_TimerA_setClockConfig(
        PWM_0_INST, (DL_TimerA_ClockConfig *) &gPWM_0ClockConfig);

    DL_TimerA_initPWMMode(
        PWM_0_INST, (DL_TimerA_PWMConfig *) &gPWM_0Config);

    // Set Counter control to the smallest CC index being used
    DL_TimerA_setCounterControl(PWM_0_INST,DL_TIMER_CZC_CCCTL0_ZCOND,DL_TIMER_CAC_CCCTL0_ACOND,DL_TIMER_CLC_CCCTL0_LCOND);

    DL_TimerA_setCaptureCompareOutCtl(PWM_0_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW,
		DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_FUNCVAL,
		DL_TIMERA_CAPTURE_COMPARE_0_INDEX);

    DL_TimerA_setCaptCompUpdateMethod(PWM_0_INST, DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE, DL_TIMERA_CAPTURE_COMPARE_0_INDEX);

    DL_TimerA_setCaptureCompareOutCtl(PWM_0_INST, DL_TIMER_CC_OCTL_INIT_VAL_LOW,
		DL_TIMER_CC_OCTL_INV_OUT_DISABLED, DL_TIMER_CC_OCTL_SRC_FUNCVAL,
		DL_TIMERA_CAPTURE_COMPARE_1_INDEX);

    DL_TimerA_setCaptCompUpdateMethod(PWM_0_INST, DL_TIMER_CC_UPDATE_METHOD_IMMEDIATE, DL_TIMERA_CAPTURE_COMPARE_1_INDEX);
    PWM_0_INST->COUNTERREGS.CCCTL_01[0]=0x60000000;//Configuring CC3 as the secondary event for CC0
    PWM_0_INST->COUNTERREGS.CCCTL_01[1]=0x80000000;//Configuring CC4 as the secondary event for CC1
    PWM_0_INST->COUNTERREGS.CCCTL_23[0]=0xA0000000;//Configuring CC5 as the secondary event for CC2

    PWM_0_INST->COUNTERREGS.CCACT_01[0]=0x00001080;//Configuring CC2DACT to drive PWM High and CDACT to drive PWM Low
    PWM_0_INST->COUNTERREGS.CCACT_01[1]=0x00001080;//Configuring CC2DACT to drive PWM High and CDACT to drive PWM Low
    PWM_0_INST->COUNTERREGS.CCACT_23[0]=0x00001080;//Configuring CC2DACT to drive PWM High and CDACT to drive PWM Low

    DL_TimerA_setCaptureCompareValue(PWM_0_INST, 5000, DL_TIMER_CC_0_INDEX);
    DL_TimerA_setCaptureCompareValue(PWM_0_INST, 4000, DL_TIMER_CC_1_INDEX);
    DL_TimerA_setCaptureCompareValue(PWM_0_INST, 3000, DL_TIMER_CC_2_INDEX);
    DL_TimerA_setCaptureCompareValue(PWM_0_INST, 9500, DL_TIMER_CC_3_INDEX);
    DL_TimerA_setCaptureCompareValue(PWM_0_INST, 9000, DL_TIMER_CC_4_INDEX);
    DL_TimerA_setCaptureCompareValue(PWM_0_INST, 8000, DL_TIMER_CC_5_INDEX);

    DL_TimerA_enableClock(PWM_0_INST);
    DL_TimerA_setCCPDirection(PWM_0_INST , DL_TIMER_CC0_OUTPUT | DL_TIMER_CC1_OUTPUT |DL_TIMER_CC2_OUTPUT);
}

Figure 3-3 shows the shifted PWM output waveforms. To dynamically change the period/duty cycle, refer to Section 8.

Phase Shifted PWM Generation Using TIMA0 Secondary EventsFigure 3-3 Phase Shifted PWM Generation Using TIMA0 Secondary Events