SDAA286 March   2026 MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Idle-Low State: PWM Output Channel Low-state Configuration
  6. Asymmetric PWM: Dual Synchronized PWM Generation with Phase Shift Control
    1. 3.1 Using Phase Load Functionality
      1. 3.1.1 Configuration for the Primary Timer (Main Timer)
      2. 3.1.2 Configuration for the Secondary Timer
      3. 3.1.3 Implementation for Cross Trigger Function
    2. 3.2 Using Secondary Capture-Compare Channels
  7. Bit-Banging Emulation: Software-based Communication Protocol Implementation
    1. 4.1 Emulation of UART Rx Using TIMA
    2. 4.2 Emulation of UART Tx Using TIMA
  8. Feedback-Based PWM Generation
    1. 5.1 Feedback-Based PWM Signal Replication
    2. 5.2 Delayed PWM Signal Generation Using an Input Reference
  9. Delayed Timer Start: Synchronized Timer Instances Initiation with Configurable Delays
  10. Stopping a Running Timer Based on Hardware Events
  11. Dynamic PWM Update: Duty Cycle and Time Period Adjustment
    1. 8.1 Shadow Load and Shadow Compare Features
    2. 8.2 Arbitrary Signal Generation with DMA
  12. Summary
  13. 10References

Feedback-Based PWM Signal Replication

The ability to generate an exact copy of an input PWM signal serves critical functions in modern electronic systems, particularly in applications requiring safety redundancy validation. This methodology finds extensive implementation in dual-channel motor control systems, where signal validation and fault detection are paramount for operational safety.

In industrial and safety-critical applications, PWM signal replication enables robust redundant control paths and continuous system monitoring. The technique involves capturing input PWM signal's characteristics and generating an identical output signal, maintaining precise timing relationships.

This capability proves especially valuable in power electronics applications, where synchronized switch control and multiple phase-aligned outputs are essential. The implementation allows for signal buffering, regeneration, and fan-out to multiple subsystems while maintaining signal integrity and noise immunity.

In motor control applications, this approach enables redundant gate drive signals and dual-channel safety systems, critical for fault-tolerant operation. The system continuously monitors and validates signals, providing real-time verification and performance monitoring capabilities. This is particularly important in industrial equipment where safety and reliability are paramount.

The implementation is straightforward yet powerful, utilizing timer capture features to read input PWM parameters and generate identical output signals. This ensures precise replication of both period and duty cycle values, maintaining signal integrity throughout the system. The resulting solution offers comprehensive benefits including signal validation, safety redundancy, distributed control capabilities, and robust system monitoring functions.

A Timer instance can be configured to generate feedback based PWM using the following steps:

  • Configure Timer in up-counting mode.
  • Configure CC0 channel for Edge Capture for both rising and falling edges.
  • Input the reference PWM signal on the CC0 channel.
  • Configure CC1 in output mode to generate feedback-based PWM.
  • Configure CCCTL.CC2SELU for CC1 channel as CC0 and CCACT.CC2UACT field as CCP output toggle. This will toggle the CC1 output based on CC0 capture events.
  • Capture event on CC0 channel will be generated by the input reference signal.
/* Configuration Sequence to Generate Feedback-based PWM */
static const DL_TimerA_ClockConfig gCAPTURE_0ClockConfig = {
    .clockSel    = DL_TIMER_CLOCK_BUSCLK,
    .divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
    .prescale = 0U
};

static const DL_TimerA_CaptureConfig gCAPTURE_0CaptureConfig = {
    .captureMode    = DL_TIMER_CAPTURE_MODE_EDGE_TIME_UP,
    .period         = CAPTURE_0_INST_LOAD_VALUE,
    .startTimer     = DL_TIMER_STOP,
    .edgeCaptMode   = DL_TIMER_CAPTURE_EDGE_DETECTION_MODE_EDGE,//Enable Edge Capture on both rising and falling edges for CC0
    .inputChan      = DL_TIMER_INPUT_CHAN_0,
    .inputInvMode   = DL_TIMER_CC_INPUT_INV_NOINVERT,
};

SYSCONFIG_WEAK void SYSCFG_DL_CAPTURE_0_init(void) {

    DL_TimerA_setClockConfig(CAPTURE_0_INST,
        (DL_TimerA_ClockConfig *) &gCAPTURE_0ClockConfig);

    DL_TimerA_initCaptureMode(CAPTURE_0_INST,
        (DL_TimerA_CaptureConfig *) &gCAPTURE_0CaptureConfig);
    DL_TimerA_setCounterControl(CAPTURE_0_INST,DL_TIMER_CZC_CCCTL0_ZCOND,DL_TIMER_CAC_CCCTL0_ACOND,DL_TIMER_CLC_CCCTL0_LCOND);

    DL_TimerA_enableInterrupt(CAPTURE_0_INST , DL_TIMERA_INTERRUPT_CC0_UP_EVENT);

    CAPTURE_0_INST->COUNTERREGS.CCACT_01[1]=0x00018000;//Enable CC output Toggle for Secondary CC event. Secondary Event for CC1 will be generated when CC0 captures an edge
    DL_TimerA_setCaptureCompareValue(CAPTURE_0_INST, 0, DL_TIMER_CC_1_INDEX);
    DL_TimerA_enableClock(CAPTURE_0_INST);
    DL_TimerA_setCCPDirection(CAPTURE_0_INST , DL_TIMER_CC1_OUTPUT);
}

The configurations above are for a scenario where the period as well as the duty cycle of the reference PWM is changing.

 Only Duty Cycle of the Reference PWM Is ChangingFigure 5-1 Only Duty Cycle of the Reference PWM Is Changing
 Both Duty Cycle and the Time Period of the Reference PWM Is ChangingFigure 5-2 Both Duty Cycle and the Time Period of the Reference PWM Is Changing