SDAA286 March   2026 MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Idle-Low State: PWM Output Channel Low-state Configuration
  6. Asymmetric PWM: Dual Synchronized PWM Generation with Phase Shift Control
    1. 3.1 Using Phase Load Functionality
      1. 3.1.1 Configuration for the Primary Timer (Main Timer)
      2. 3.1.2 Configuration for the Secondary Timer
      3. 3.1.3 Implementation for Cross Trigger Function
    2. 3.2 Using Secondary Capture-Compare Channels
  7. Bit-Banging Emulation: Software-based Communication Protocol Implementation
    1. 4.1 Emulation of UART Rx Using TIMA
    2. 4.2 Emulation of UART Tx Using TIMA
  8. Feedback-Based PWM Generation
    1. 5.1 Feedback-Based PWM Signal Replication
    2. 5.2 Delayed PWM Signal Generation Using an Input Reference
  9. Delayed Timer Start: Synchronized Timer Instances Initiation with Configurable Delays
  10. Stopping a Running Timer Based on Hardware Events
  11. Dynamic PWM Update: Duty Cycle and Time Period Adjustment
    1. 8.1 Shadow Load and Shadow Compare Features
    2. 8.2 Arbitrary Signal Generation with DMA
  12. Summary
  13. 10References

Delayed Timer Start: Synchronized Timer Instances Initiation with Configurable Delays

Timers with intentional start-time offsets enable controlled phase relationships that are critical for efficiency, stability and signal integrity in some applications involving motor control, and sensor data polling or sampling. This can be achieved when using two or more timers by using them in synchronized fashion using the cross-triggering mechanism, as described below:

  • Configure the timers in a software based cross-triggering mechanism, as per Section 3.
  • Based on the application the timer that is to be enabled first can be configured as the primary timer.
  • Configure CC value depending on the required start-time offsets.
  • Generate a Software Cross-Trigger within the CC event ISR to enable the Secondary Timer.
    Note:

    Due to delay limitations that prevent setting delays on the second Timer when specific duty cycles are required for the first PWM output, using the CC4/5 event of the first PWM would provide the necessary flexibility for configuring the delay.

For example, an offset of 10ms is needed between enabling TIMA0 and TIMA1. If TIMA1 is required to be enabled first, configure TIMA1 as the primary timer and TIMA0 as the secondary timer. Configure the CC value for TIMA1 such that CC event is generated exactly 10ms after enable. Within this CC event a Software Cross Trigger can be generated to enable TIMA0 exactly after 10ms. This means, with CLKSEL as LFCLK (32KHz) TIMA1's CC value can be configured as 320 with Timer in Up Counting mode, this will generate a CC event after ~10ms (320 cycles × (1/32000) seconds = 0.01 seconds = 10ms). This CC event will enable TIMA0 via the software based cross-triggering mechanism.
/* TIMA Interrupt Service Routine */
void PWM_0_INST_IRQHandler(void)
{
    switch (DL_TimerA_getPendingInterrupt(PWM_0_INST)) {
        case DL_TIMERA_IIDX_CC0_DN:
            if(interrupt_counter==0){
            DL_TimerA_generateCrossTrigger(PWM_0_INST);//Mechanism to generate Software based Cross-Trigger
            }
            else{
				;
            }
            interrupt_counter++;
            break;
        default:
            break;
    }
}
Note:

While the Hardware Cross-Triggering functionality can also be utilized for this application, it is important to recognize that this mechanism will generate Cross-Trigger on every CC event. Therefore, if developers intend to utilize the hardware cross-trigger capability, it must be explicitly disabled after one cross-trigger for this application to function as intended.

 Configurable Timer Start Time OffsetFigure 6-1 Configurable Timer Start Time Offset