SDAA236 March   2026 DS90UB960-Q1

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2ADAS FPD-Link III Deserializer Overview
  5. 3MIPI CSI-2 Overview
    1. 3.1 MIPI CSI-2 Frame Break Down
    2. 3.2 MIPI CSI-2 Overhead Introduction
  6. 4CSI-2 Input Bandwidth Calculation
  7. 5CSI-2 Output Bandwidth Calculation
    1. 5.1 CSI-2 Aggregation Overview
    2. 5.2 CSI-2 Output Bandwidth Calculation
  8. 6Summary
  9. 7References

3.2 MIPI CSI-2 Overhead Introduction

Between long and short packets, and between different long packets, the CSI-2 transmitter must enter low-power state (LPS). The transmitter is also required to transition from Low-Power to High-Speed signaling mode. During the LPS and time associated with the transition, the transmitter is idle and no data packets that can be sent, which means the CSI-2 output bandwidth is reduced.

The minimum CSI-2 High-Speed data transmission overhead consists of TLPX, THS-PREPARE, THS-ZERO, THS-SYNC, THS-TRAIL, and THS-EXIT as shown in Figure 3-3. The bandwidth is further reduced when operating in discontinuous CSI-2 Clock mode as it brings more CSI-2 overhead since data also cannot be sent while the clock lane is either in LP mode or transiting to HS mode, as shown in Figure 3-4.

Switching the Clock Lane Between Clock Transmission and Low-Power Mode Figure 3-4 Switching the Clock Lane Between Clock Transmission and Low-Power Mode
High Speed Data Transmission Burst Figure 3-5 High Speed Data Transmission Burst