SDAA236 March   2026 DS90UB960-Q1

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2ADAS FPD-Link III Deserializer Overview
  5. 3MIPI CSI-2 Overview
    1. 3.1 MIPI CSI-2 Frame Break Down
    2. 3.2 MIPI CSI-2 Overhead Introduction
  6. 4CSI-2 Input Bandwidth Calculation
  7. 5CSI-2 Output Bandwidth Calculation
    1. 5.1 CSI-2 Aggregation Overview
    2. 5.2 CSI-2 Output Bandwidth Calculation
  8. 6Summary
  9. 7References

Introduction

FPD-Link III deserializer devices are capable of aggregating video streams from either two or four incoming serializers to the processors with MIPI CSI-2 interface. CSI-2 protocol divides video data into packets at a line level so the line length of each image sensor is a critical factor in determining the aggregated bandwidth at the deserializer output. During the transmission of data on the CSI-2 port, the D-PHY output port will transition between low power (LP) and high speed (HS) modes. In HS mode, CSI-2 data packets will be transmitted such as long packets (each long packet contains a single video line) and short packets (containing video timing information like frame start and frame end). In LP mode, the interface is idle with no data being sent on the interface. This application note will provide an overview of MIPI CSI-2 as it relates to camera SerDes, break down the details of FPD-Link III deserializer CSI-2 aggregation capabilities and provide the guidance on how to evaluate FPD-Link deserializer devices’ input and output bandwidth.