3 HS Device Flashing Without Boot Mode Switch

If a jig-free and no-manual burning Keywriter method can be implemented on the production line that can support secure boot, that is significant to customers that must implement secure boot. TI's processors support redundant boot modes and redundant OSPI boot offset mechanisms. This application note leverages this mechanism to provide several designs to the problem.

Primary OSPI Offset and Backup OSPI Offset

The OSPI protocol is described according to bit-width (one or eight) and data rate (Single Data Rate (S) or Double Data rate (D)) for the Command/Address/Data segments of the protocol. The OSPI boot mode supports 1S-1S-8S mode. The Command and Address issued are eight bits and 24 bits respectively. The Read Command that is issued for OSPI mode is 0x8B followed by zero for address and eight dummy cycles. The frequency of operation supported is 50MHz. In the OSPI boot mode, the ROM code initializes the OSPI module and the image is read from the OSPI flash connected to the selected chip-select. If the image fails to be read correctly from offset 0x0 of the flash memory, the ROM attempts to obtain the image at offset 0x400000. This is the only redundant image location supported by the ROM. ROM code first copies boot image into on-chip RAM and then executes the image.

Primary Boot Mode and Backup Boot Mode

The DMSC is the boot controller for the Public ROM. DMSC performs the required configurations and releases the reset to R5.

R5 checks primary boot mode media and checks image integrity. If primary boot mode fails, then R5 changes to backup boot mode and checks image integrity.