SDAA081 September   2025 DP83825I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Troubleshooting the Application
    1. 2.1 Schematic Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
      4. 2.3.4 Compliance
    4. 2.4 RMII Health Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Summary
  7. 4References

2.2.5 Probe the Strap Pins During Initialization

The DP83825 has strap pins for configuring the device in a predetermined mode. The voltage at these strap pins determines which mode the DP83825 can operate in.

On initialization, the external strap network along with the internal resistor creates a voltage divider that the PHY samples. No other component on the line needs to affect the DC bias set by this network.

DP83825 Strap Circuit Figure 2-3 DP83825 Strap Circuit
DP83825 LED Strap Circuit Figure 2-4 DP83825 LED Strap Circuit

In some cases, other devices on the board (for example, the MAC) can drive the strap pins unexpectedly. The strap values can be read from registers 0x0467 (SOR1) and 0x0468 (SOR2). If there is power cycle dependency to an issue, the strapping can be marginal and can be observed cycle to cycle against these registers to determine if the PHY is strapped in an unintended state.

Measurements can be made during power up and after power up when the RESET_N signal is asserted.