SBVU074 November   2021

 

  1. 1Trademarks
  2. 2Introduction
  3. 3Setup
    1. 3.1 LDO Input/Output Connector Descriptions
      1. 3.1.1 VIN and GND
      2. 3.1.2 BIAS and GND
      3. 3.1.3 VOUT and GND
      4. 3.1.4 EN
    2. 3.2 Optional Load Transient Input/Output Connector Descriptions
      1. 3.2.1 VDD and GND
      2. 3.2.2 J13
      3. 3.2.3 J15
      4. 3.2.4 J16
      5. 3.2.5 J18
      6. 3.2.6 J19
      7. 3.2.7 J22
      8. 3.2.8 TP2,TP3, and TP4
      9. 3.2.9 TP5
    3. 3.3 TPS7A13 LDO Operation
    4. 3.4 Optional Load Transient Circuit Operation
  4. 4Board Layout
  5. 5TPS7A13 EVM Schematic
  6. 6Bill of Materials

4 Board Layout

Figure 4-1 through Figure 4-6 show the board layout for the TPS7A13EVM-057 PCB.

The TPS7A13EVM-057 dissipates power, which may cause some components to experience an increase in temperature. The TPS7A13 LDO, LMG1020YFFR gate driver, and pulsed resistors R2, R3, R4, R5, and R6 are most at risk of raising to a high junction temperature during normal operation.

Figure 4-1 Top Assembly Layer and Silk Screen
Figure 4-3 Layer 2
Figure 4-5 Bottom Layer Routing
Figure 4-2 Top Layer Routing
Figure 4-4 Layer 3
Figure 4-6 Bottom Assembly Layer and Silk Screen