3 Test Device and Test Board Information

The SN55LVTA4-SEP is a packaged 16-pin, SOIC plastic package shown in the pinout diagram in Figure 3-1. Figure 3-2 shows the device with the package cap decapped to reveal the die for heavy ion testing. Figure 3-3 shows the evaluation board used for radiation testing. Figure 3-4 shows the bias diagram used for Single-Event Latch-up (SEL) testing. Figure 3-5 and Figure 3-4 show the bias diagrams used for Single-Event Transient (SET) testing.

Figure 3-1 SN55LVTA4-SEP Pinout Diagram

Figure 3-2 Photo of SN55LVTA4-SEP Package Decapped

Figure 3-3 SN55LVTA4-SEP Evaluation Board (Top View)

Figure 3-4 SN55LVTA4-SEP SEL Bias Diagram

Figure 3-5 SN55LVTA4-SEP SET Bias Diagram