Design Objective

Objective: Generation of a ±15V precision supply from a +5V source.

Design Description

Some precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) require high-voltage supplies for operation. This analog engineer’s circuit describes a precision, high-voltage supply circuit that can be used for high-voltage precision data converters. In this design, a push-pull driver first boosts a +5V supply input to approximately ±20V using an off-the-shelf center-tapped transformer. Following this output, a dual output low-dropout (LDO) voltage regulator sets an output for ±15V supplies. Many applications like programmable logic controllers (PLCs), analog inputs, and analog outputs require high voltages for either input measurement or output drive.

Design Notes

1. This circuit is driven by the 5V nominal supply from a USB host port. Care must be taken to make sure the USB voltage is high enough and to prevent surpassing the USB port current limit.
   1. USB 1.0, 1.1, and 2.0 have a voltage output with a minimum of 4.75V. With USB-C at high currents, this voltage can be as low as 4.5V.
   2. USB 1.0, 1.1, and 2.0 have a current output capability of 500mA. Some charging ports for USB can offer higher current outputs. A USB-C port can output up to 3A.
   3. If the source output voltage is lower than expected, a buck-boost circuit can be added to the input for proper operation.
2. The high-voltage output is derived from the 5V supply that comes from a transformer driven by the SN6505B. The SN6505B low-noise transformer driver targets small form factor, isolated power supplies and drives low-profile, center-tapped transformers from a 2.25V to 5.5V dc power supply. This transformer driver operates in a push-pull converter to multiply the input voltage.
3. The basic structure of the push-pull converter is shown in the following circuit diagram, where the transformer turns are approximately n = 2. This boosts the 5V input to approximately ±20V.
   

   The SN6505B creates cycles from switching D1 and D2. These cycles push or pull current through the center-tap transformer. The switching cycles alternate to set the positive and negative voltage output beyond the rectifier diodes. The figure below shows the current path through the output during the switching cycles.

   
4. The SN6505B precision internal oscillator nominally runs at 420kHz, but if this frequency interferes with other circuitry on the board, an external oscillator can be used. Another option uses the similar SN6505A which has a 160kHz internal oscillator.
5. Set up the SN6505B transformer driver with the following considerations:
   1. Use a low equivalent series resistance (ESR) bypass capacitor of 4.7µF or greater at the input of the transformer driver.
   2. Use bulk capacitors at the rectifier output from 1µF to 10µF.
   3. To prevent the transformer operation in saturation, check the V-t product for the transformer using the SN6505B operating parameters. The transformer minimum V-t product calculates from the maximum voltage that the device delivers and the maximum time of each switching cycle. The maximum voltage is calculated by using the nominal converter input of 5V and adding 10%. The maximum time this voltage is applied to the primary is half of the period of the lowest frequency. For the SN6505B, the minimum frequency from the internal oscillator is 363kHz. The V-t product for the SN6505B is calculated to be 7.6V-µs.
      ${\mathrm{V}\mathrm{t}}_{\mathrm{m}\mathrm{i}\mathrm{n}}\ge {\mathrm{V}}_{\mathrm{I}\mathrm{N}\mathrm{m}\mathrm{a}\mathrm{x}}\times \frac{{\mathrm{t}}_{\mathrm{m}\mathrm{a}\mathrm{x}}}{2}=\frac{{\mathrm{V}}_{\mathrm{I}\mathrm{N}\mathrm{m}\mathrm{a}\mathrm{x}}}{2\times {\mathrm{f}}_{\mathrm{m}\mathrm{i}\mathrm{n}}}$
      ${\mathrm{V}\mathrm{t}}_{\mathrm{m}\mathrm{i}\mathrm{n}}\ge \frac{5.5\mathrm{V}}{2\times 363\mathrm{k}\mathrm{H}\mathrm{z}}=7.6\mathrm{V}\text{-}\mathrm{\mu }\mathrm{s}$
   4. The recommended transformer is a Würth Elektronik® 760390015 transformer with an inductance of 475µH. The V-t product for this transformer is 11V-µs which is higher than the previously calculated 7.6V-µs V-t product. The turns ratio from N1 + N2:N3 + N4 is 1:2. This transformer is listed in SN6505x Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet in the recommended isolation transformers optimized for the device table.
   5. Use low forward-voltage Schottky diodes with high reverse-breakdown voltages. The MBR0580-TP (with an 80V reverse breakdown) is selected for this circuit.
   6. The minimum current clamp limit for the SN6505B is 1.42A. This clamp limits the current going into the transformer. However, the transformer data sheet output current plots show a maximum current of 0.7A. Testing of this circuit is limited to 500mA.
6. After the ±20V boost circuit is constructed, the TPS7A3901 dual positive and negative LDO is used to generate the ±15V supply outputs. For more information about this LDO, see the TPS7A39 Dual, 150mA, Wide V_IN Positive and Negative LDO Voltage Regulator data sheet.
   1. The LDO maximum output is limited to 150mA (sourcing current from the positive output and sinking current from the negative output). However, this circuit is tested to a maximum of 50mA output.
   2. The EN pin acts as a power good to enable the LDO. The minimum enable voltage is 2.2V. The voltage at the EN pin is derived from a 499kΩ to 100kΩ resistor voltage divider from the positive 20V output from the transformer.
   3. The output of the LDO is adjustable using a resistor divider to a feedback input pin. The feedback input for the positive LDO is set at the FBP pin. The output is set by determining the resistor divider from the output voltage to get V_FBP to be 1.188V. The following diagram shows the positive LDO output.
      
      Starting with the output at 15V and a 10kΩ resistor from FBP to ground, the top resistor can be calculated from:
      $\left(\frac{{\mathrm{R}}_1+10\mathrm{k}\mathrm{\Omega }}{10\mathrm{k}\mathrm{\Omega }}\right)\times 1.188\mathrm{V}=\mathrm{ }15\mathrm{V}$
      ${\mathrm{R}}_1=(12.62\mathrm{ }\times 10\mathrm{k}\mathrm{\Omega })-10\mathrm{k}\mathrm{\Omega }$
      ${\mathrm{R}}_1=116.2\mathrm{k}\mathrm{\Omega }$
      R1 is selected to be 118kΩ, using a 1% standard resistor value. This gives a positive LDO output value of 15.21V.
   4. Similarly, the negative LDO output is derived from a voltage divider from the output buffer of the internal voltage reference at the BUF pin. The feedback input for the negative LDO is set at the FBN pin. This V_FBN voltage is typically 3.7mV.
      
      Starting with the output at –15V and a 10kΩ resistor from BUF to FBN, the bottom resistor can be calculated from:
      $\frac{{\mathrm{R}}_2}{10\mathrm{k}\mathrm{\Omega }}\left(1.19\mathrm{V}-3.7\mathrm{m}\mathrm{V}\right)+3.7\mathrm{m}\mathrm{V}=-15\mathrm{V}$
      ${\mathrm{R}}_2=\frac{\left(15\mathrm{V}-3.7\mathrm{m}\mathrm{V}\right)\times 10\mathrm{k}\mathrm{\Omega }}{1.1863\mathrm{V}}$
      ${\mathrm{R}}_2=126.4\mathrm{k}\mathrm{\Omega }$
      R2 is selected to be 127kΩ, using another 1% standard resistor value. This gives a value of approximately –15V for the negative LDO. The nominal value from this setup is calculated to be –15.07V.
   5. The TPS7A3901 positive dropout voltage is typically 175mV, with a maximum of 300mV. The negative dropout voltage is typically –145mV, with a minimum of –250mV. Both these dropout voltages are specified sourcing 50mA and sinking 50mA respectively.
   6. The CNR/SS pin is used to reduce low frequency noise. A capacitor of 10nF is selected for this pin. CFFP and CFFN capacitances can be used to reduce mid-frequency noise.
   7. While this application is drawn as an non-isolated supply, the circuit can be applied as an isolated supply for industrial applications by separating the grounds on either side of the transformer.

Measured Results

The circuit underwent testing from the dual supply on the ADS125H02EVM. While this evaluation module targets a precision ADC, this supply can also be implemented for precision DACs, such as the DAC81404 or DAC8760.

A 5V supply provides the input. The output voltage of the push-pull converter is measured at the input of the LDO. The output of the LDO is also measured. The results of these measurements are listed in the following table.

Because the output voltage exceeds the input voltage significantly, the output load current remains much smaller than the input current. The TPS7A3901 dual LDO is tested with resistive loads, sourcing current from the positive LDO output and sinking current from the negative LDO output. The plot below shows the relation between the input current from the 5V supply and the output current load of the ±15V supplies.

Based on measurements of the constructed circuit, the input current is over eight times larger than the output load current. For a standard USB 2.0 port sourcing 500mA, the maximum output current of the ±15V supplies reaches approximately 60mA.

Additionally, the circuit output efficiency undergoes measurement. The input power is calculated from the 5V supply and the supply current is recorded. Then the output power is calculated from the ±15V supply and the output load current is also recorded. These values are plotted at different output loads for the power efficiency. The efficiency is measured to be 73% with a load current of 50mA for this circuit. Efficiency results are shown in the following plot.

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Design References

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Additional Resources

• Texas Instruments, ADS125H02 Evaluation Module User's Guide
• Texas Instruments, Isolated Power Topologies for PLC I/O Modules and Other Low-Power Applications Product Overview
• Texas Instruments, Powering a dual-supply op-amp circuit with one LDO
• Texas Instruments, Precision labs series: Digital-to-analog converters (DACs)
• Texas Instruments, Precision labs series: Analog-to-digital converters (ADCs)

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