SBOA550 October   2022 OPA1671 , OPA2990 , SN74HCS04 , SN74HCS164 , SN74HCS30 , SN74LVC1G00 , SN74LVC1G123 , TLC04 , TLC14 , TS5A9411

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 The Davies Generator
  5. 3 Optimizing Standard Resistance Values for THD Performance
  6. 4 Simulation Examples
  7. 5 Compensating for Shift Register Output Resistance
  8. 6 Voltage-Mode Thevenin Equivalent
  9. 7 Harmonic Filtering
  10. 8 Tracking Harmonic Filter
  11. 9 Multiphase Output
  12. 10Conclusion
  13. 11Acknowledgment
  14. 12References
  15.   A Analytical Solution for Resistance Network Values
  16.   B Forbidden States of the Johnson Counter

5 Compensating for Shift Register Output Resistance

The SN74HCS164 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs data sheet provides insight into the output resistance of the flip-flops, with the output driver specifications shown in Figure 5-1.

GUID-20220711-SS0I-FCBD-WZ7F-TMNWMJMS3JRP-low.png
Register, RO appears to be ≈ 31.7 Ω sourcing or sinking with VCC = 4.5 V.
Figure 5-1 Output Drive Specification for the SN74HCS164 Shift Register

For sourcing current, the output resistance typically is (4.5 V – 4.3 V) / 0.006 A ≈ 33.3 Ω. For sinking current, the typical output resistance is 0.18 V / 0.006 A ≈ 30.0 Ω. The average output resistance is then approximately 31.7 Ω, which is about 1% of the value of the inner resistors of the previous idealized case; significant given the level of THD so far in question. Note that the worse case MIN, MAX values are dramatically different and result in much higher and more asymmetric output resistance values.

Recalculating the resistor network by assuming the previously discussed typical output resistance, the following network and an overall Thevenin output resistance of 597.6 Ω is determined. Using the same FFT analysis the THD for this compensated version is < 0.06%, and the 3rd harmonic is 65 dB below the fundamental. This is nearly a 8-dB improvement in 3rd harmonic performance compared to Figure 4-3, obtained simply by optimizing the resistor values to account for average output resistance.

THD calculation < 0.06% for simulation using these values.
Figure 5-2 Recalculated E96 Resistor Values Compensate for Average (About 31.7 Ω) Flip-Flop Output Resistance

Alternatively, the effects of output resistance can be reduced (though not eliminated) by simply scaling up the Thevenin resistance of the whole network – the previous example uses a relatively low Thevenin resistance to accentuate the impact of flip-flop resistance on THD.