SBAU442A December   2023  – December 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  8. 2Hardware
    1. 2.1 Board Overview
    2. 2.2 Required Equipment
    3. 2.3 Hardware Modifications
    4. 2.4 Hardware Setup
  9. 3Software
    1. 3.1 Software Setup
  10. 4Implementation Results
    1. 4.1 Bringup
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6References
  13. 7Revision History

1.1 Introduction

The ADC3910D125EVM allows for evaluation of all ADC39XX versions as the versions are all P2P compatible. By default, the ADC3910D125EVM, has the ADC3910D125 (10-bit, 125MSPS). The EVM is configured to receive external single-ended analog inputs as the EVM includes baluns for single-ended to differential conversion. The sample clock is also sourced externally and is single-ended LVCMOS.

To capture data from the ADC3910D125EVM, the EVM is connected to a TSWDC155EVM through an FMC connector. The TSWDC155EVM has an AMD Atrix-7 FPGA to capture the ADC3910D125EVM output. The ADC data, captured by the FPGA, is then transferred to the PC and displayed in HSDC Pro.