Each common-mode tolerance mode achieves good common-mode rejection up to the limits of that mode. The graphs in Figure 2-2 show FFTs of the ADC output on a on a TAC5212EVM-K, with a 1kHz AC common-mode signal given to the inputs along with a common-mode DC bias voltage. Figure 2-2 (a) is the FFT when the common-mode swing is at 50mV_pp which is within the tolerable limit of 100mV_pp (35.36mVrms, which corresponds to -35.05dBFS for a 2Vrms full-scale swing). Figure 2-2 (b) is the FFT when the common-mode swing is at tolerance limit of 100mV_pp. Figure 2-2 (c) is the FFT when the common-mode swing exceeds the tolerance limit of 100 mV_pp.

Similarly, Figure 2-3 and Figure 2-4 show the FFTs for the TAC5212 output on the TAC5212EVM-K when the device is configured in CM_TOL of 1 and 2 respectively.

CMRR for the TAx511x/TAx511x-Q1 devices in mode 0 is 60dB(typ) and typically changes by a few dB in modes 1 and 2 for an equivalent signal amplitude. The higher performance TAx521x and TAx521x-Q1 can achieve a CMRR closer to 80dB (typ) in mode 2 and is a good choice for systems that want the best performance possible in applications that require high common-mode tolerance. The variation of CMRR across different levels of input common-mode swing is plotted in Figure 2-5 for a 1kHz common-mode signal. The AC signal level is varied from 50mVpp to 2.75Vpp, with a common-mode DC bias voltage. The CMRR in Figure 2-5 is averaged across both input channels on a TAC5212EVM-K.

Note that mismatches in the external differential signal path (trace impedance, AC-coupling capacitor tolerance etc.) also contribute to the CMRR seen at the ADC output. Figure 2-6 shows the variation in CMRR across frequency on the TAC5212EVM-K when the inputs are AC-Coupled with 10µF capacitors whose tolerance is up to +/-20%, and when the inputs are DC-Coupled. The measurement was taken with a 100mV_p-p common-mode signal level. The CMRR in Figure 2-6 is averaged across both input channels.