SBAA461 December   2020 ADC3541 , ADC3542 , ADC3543 , ADC3544 , ADC3641 , ADC3642 , ADC3643 , ADC3644 , ADC3660 , ADC3681 , ADC3682 , ADC3683

 

  1.   Trademarks
  2. 1Introduction
  3. 2Reduce Data Rates: Optimize Pin Count and Data Rate
    1. 2.1 Parallel CMOS
      1. 2.1.1 Parallel SDR
      2. 2.1.2 Parallel DDR
    2. 2.2 Serial CMOS
      1. 2.2.1 2 Wire
      2. 2.2.2 1 Wire
      3. 2.2.3 0.5 Wire
  4. 3Reduce Data Rates: Decimation
  5. 4Summary
  6. 5References

2.2.2 1 Wire

In 1 Wire mode, all 14 bits of one channel are being transmitted on one wire. With the DCLK and FCLK, this is a total of 4 output pins/resistors.

GUID-20201203-CA0I-SHQ9-QXCH-DDW8XTSQRR52-low.png Figure 2-7 ADC3643 Serial CMOS: 1 Wire Resistors

A total of 14 bits on one wire will be transmitted over one frame clock period, so the serialization rate is 14x times the sampling rate. The data rate is limited to ~250 Mbps due to the CMOS interface, so the max sampling rate in this mode is 35 MSPS. Higher sampling rates can be used when decimation is used.

Table 2-5 1 Wire Serial CMOS (No Decimation)
Mode Max Sampling Rate (MSPS) Serialization Rate Data Rate (Mbps) Data Outputs/ Resistors
1 Wire 17.8 14 250 4
GUID-20201102-CA0I-KJQC-HH2B-PVDZCXQQDXCC-low.png Figure 2-8 Serial CMOS 1W Timing Diagram