ZHCSK78 September   2019 BQ21061

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Linear Charger and Power Path
        1. 7.3.1.1 Battery Charging Process
        2. 7.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 7.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 7.3.1.4 Battery Supplement Mode
      2. 7.3.2  Protection Mechanisms
        1. 7.3.2.1 Input Over-Voltage Protection
        2. 7.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 7.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 7.3.2.4 Battery Short and Over Current Protection
        5. 7.3.2.5 PMID Short Circuit
      3. 7.3.3  VDD LDO
      4. 7.3.4  Load Switch/LDO Output and Control
      5. 7.3.5  PMID Power Control
      6. 7.3.6  System Voltage (PMID) Regulation
      7. 7.3.7  MR Wake and Reset Input
        1. 7.3.7.1 MR Wake or Short Button Press Functions
        2. 7.3.7.2 MR Reset or Long Button Press Functions
      8. 7.3.8  14-Second Watchdog for HW Reset
      9. 7.3.9  Faults Conditions and Interrupts (INT)
        1. 7.3.9.1 Flags and Fault Condition Response
      10. 7.3.10 Power Good (PG) Pin
      11. 7.3.11 External NTC Monitoring (TS)
        1. 7.3.11.1 TS Thresholds
      12. 7.3.12 I2C Interface
        1. 7.3.12.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
      2. 7.4.2 Low Power
      3. 7.4.3 Active Battery
      4. 7.4.4 Charger/Adapter Mode
      5. 7.4.5 Power-Up/Down Sequencing
    5. 7.5 Register Map
      1. 7.5.1 I2C Registers
        1. 7.5.1.1  STAT0 Register (Address = 0x0) [reset = X]
          1. Table 8. STAT0 Register Field Descriptions
        2. 7.5.1.2  STAT1 Register (Address = 0x1) [reset = X]
          1. Table 9. STAT1 Register Field Descriptions
        3. 7.5.1.3  STAT2 Register (Address = 0x2) [reset = X]
          1. Table 10. STAT2 Register Field Descriptions
        4. 7.5.1.4  FLAG0 Register (Address = 0x3) [reset = 0x0]
          1. Table 11. FLAG0 Register Field Descriptions
        5. 7.5.1.5  FLAG1 Register (Address = 0x4) [reset = 0x0]
          1. Table 12. FLAG1 Register Field Descriptions
        6. 7.5.1.6  FLAG2 Register (Address = 0x5) [reset = 0x0]
          1. Table 13. FLAG2 Register Field Descriptions
        7. 7.5.1.7  FLAG3 Register (Address = 0x6) [reset = 0x0]
          1. Table 14. FLAG3 Register Field Descriptions
        8. 7.5.1.8  MASK0 Register (Address = 0x7) [reset = 0x0]
          1. Table 15. MASK0 Register Field Descriptions
        9. 7.5.1.9  MASK1 Register (Address = 0x8) [reset = 0x0]
          1. Table 16. MASK1 Register Field Descriptions
        10. 7.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]
          1. Table 17. MASK2 Register Field Descriptions
        11. 7.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
          1. Table 18. MASK3 Register Field Descriptions
        12. 7.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]
          1. Table 19. VBAT_CTRL Register Field Descriptions
        13. 7.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]
          1. Table 20. ICHG_CTRL Register Field Descriptions
        14. 7.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]
          1. Table 21. PCHRGCTRL Register Field Descriptions
        15. 7.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]
          1. Table 22. TERMCTRL Register Field Descriptions
        16. 7.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]
          1. Table 23. BUVLO Register Field Descriptions
        17. 7.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]
          1. Table 24. CHARGERCTRL0 Register Field Descriptions
        18. 7.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0xC2]
          1. Table 25. CHARGERCTRL1 Register Field Descriptions
        19. 7.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x6]
          1. Table 26. ILIMCTRL Register Field Descriptions
        20. 7.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]
          1. Table 27. LDOCTRL Register Field Descriptions
        21. 7.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]
          1. Table 28. MRCTRL Register Field Descriptions
        22. 7.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]
          1. Table 29. ICCTRL0 Register Field Descriptions
        23. 7.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
          1. Table 30. ICCTRL1 Register Field Descriptions
        24. 7.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]
          1. Table 31. ICCTRL2 Register Field Descriptions
        25. 7.5.1.25 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
          1. Table 32. TS_FASTCHGCTRL Register Field Descriptions
        26. 7.5.1.26 TS_COLD Register (Address = 0x62) [reset = 0x7C]
          1. Table 33. TS_COLD Register Field Descriptions
        27. 7.5.1.27 TS_COOL Register (Address = 0x63) [reset = 0x6D]
          1. Table 34. TS_COOL Register Field Descriptions
        28. 7.5.1.28 TS_WARM Register (Address = 0x64) [reset = 0x38]
          1. Table 35. TS_WARM Register Field Descriptions
        29. 7.5.1.29 TS_HOT Register (Address = 0x65) [reset = 0x27]
          1. Table 36. TS_HOT Register Field Descriptions
        30. 7.5.1.30 DEVICE_ID Register (Address = 0x6F) [reset = 0x3A]
          1. Table 37. DEVICE_ID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/PMID) Capacitors
        2. 8.2.2.2 VDD, LDO Input and Output Capacitors
        3. 8.2.2.3 TS
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 具有 1.25mA 至 500mA 快速充电电流范围的线性电池充电器
    • 精度为 0.5% 的 I2C 可编程电池稳压范围为 3.6V 至 4.6V，阶跃为 10mV
    • 可配置的终止电流，支持低至 0.5mA
    • 可耐受 20V 的输入，具有 3.4V 至 5.5V 的典型输入电压工作范围
    • 可编程热负荷曲线，完全可配置的热、温、凉、冷阈值
  • 电源路径管理，用于系统供电和电池充电
    • I2C 可编程稳定系统电压 (PMID) 范围为 4.4V 至 4.9V，此外还具有电池电压跟踪功能和输入直通选项
    • 动态电源路径管理可以对通过弱适配器充电进行优化
    • 利用高级 I2C 控制，主机可以根据需要断开电池或适配器
  • I2C 可配置负载开关或高达 150mA LDO 输出
    • 可编程范围为 0.6V 至 3.7V，阶跃为 100mV
  • 超低 Iddq，可延长电池寿命
    • 10nA 运输模式电池 Iq
    • 在为系统供电时具有 400nA 的 Iq（PMID 和 VDD 打开）
  • 通过可调节计时器实现单按钮唤醒和重置输入
    • 支持系统循环通电和硬件重置
  • 20 引脚 2mm x 1.6mm CSP 封装
  • 总解决方案尺寸为 11mm2