ZHCSK78A september   2019  – august 2023 BQ21061

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Linear Charger and Power Path
        1. 7.3.1.1 Battery Charging Process
        2. 7.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 7.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 7.3.1.4 Battery Supplement Mode
      2. 7.3.2  Protection Mechanisms
        1. 7.3.2.1 Input Over-Voltage Protection
        2. 7.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 7.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 7.3.2.4 Battery Short and Over Current Protection
        5. 7.3.2.5 PMID Short Circuit
      3. 7.3.3  VDD LDO
      4. 7.3.4  Load Switch/LDO Output and Control
      5. 7.3.5  PMID Power Control
      6. 7.3.6  System Voltage (PMID) Regulation
      7. 7.3.7  MR Wake and Reset Input
        1. 7.3.7.1 MR Wake or Short Button Press Functions
        2. 7.3.7.2 MR Reset or Long Button Press Functions
      8. 7.3.8  14-Second Watchdog for HW Reset
      9. 7.3.9  Faults Conditions and Interrupts ( INT)
        1. 7.3.9.1 Flags and Fault Condition Response
      10. 7.3.10 Power Good ( PG) Pin
      11. 7.3.11 External NTC Monitoring (TS)
        1. 7.3.11.1 TS Thresholds
      12. 7.3.12 I2C Interface
        1. 7.3.12.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
      2. 7.4.2 Low Power
      3. 7.4.3 Active Battery
      4. 7.4.4 Charger/Adapter Mode
      5. 7.4.5 Power-Up/Down Sequencing
    5. 7.5 Register Map
      1. 7.5.1 I2C Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/PMID) Capacitors
        2. 8.2.2.2 VDD, LDO Input and Output Capacitors
        3. 8.2.2.3 TS
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 静电放电警告
    6. 11.6 Trademarks
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

MR Reset or Long Button Press Functions

The BQ21061 device may be configured to perform a system hardware reset (Power Cycle/Autowake), go into Ship Mode, or simply do nothing after a long button press (for example, when the MR pin is driven low until the MR_HW_RESET timer expires).The action taken by the device when the timer expires is configured through the MR_LPRESS_ACTION bits in the ICCTRL1 Register section. Once the MR_HW_RESET timer expires the device immediately performs the operation set by the MR_LPRESS_ACTION bits. The BQ21061 sends an interrupt to the host when the device detects that MR has been pressed for a period that is within tHW_RESET_WARN from reaching tHW_RESET. This may warn the host that the button has been pressed for a period close to tHW_RESET which would trigger a HW Reset or used as another button press timer interrupt like the WAKE1 and WAKE2 timers. This interrupt is sent before the MR_HW_RESET timer expires and sets the MRRESET_WARN flag. The tRESET_WARN may be set through I2C by the MR_RESET_WARN bits in the MRCTRL register. The host may change the reset behavior at any time after MR going low and prior to the MR_HW_RESET timer expiring. It may not change it however from another behavior to a HW reset (Power Cycle/Autowake) since a HW reset can be gated by other condition requirements, such as valid VIN presence (controlled by MR_RESET_VIN bit), throughout the whole duration of the button press. This flexibility allows the host to abort any reset or power shutdown to the system by overriding a long button press command.

A HW reset may also be started by setting the HW_RESET bit. Note that during a HW reset , VDD remains on.

GUID-AB4B39C2-13CF-4F62-8490-72A994A56032-low.gif Figure 7-5 MR Wake and Reset Timing with VIN Present or BAT Active Mode When MR_LPRESS_ACTION = 00
GUID-CD0EF89F-47B8-4879-A1B0-01DF84B77F47-low.gif Figure 7-6 MR Wake and Reset Timing Active Mode When MR_LPRESS_ACTION = 1x (Ship Mode) and Only BAT is Present