ZHCSC55A January   2014  – March 2014 UCD9244-EP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（继续）
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics (Continued)
    7. 7.7  ADC Monitoring Intervals And Response Times
    8. 7.8  Hardware Fault Detection Latency
    9. 7.9  PMBus/SMBus/I2C
    10. 7.10 I2C/SMBus/PMBus Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PMBus Interface
      2. 8.3.2  Resistor Programmed PMBus Address Decode
      3. 8.3.3  VID Interface
      4. 8.3.4  Jtag Interface
      5. 8.3.5  Bias Supply Generator (Shunt Regulator Controller)
      6. 8.3.6  Power-On Reset
      7. 8.3.7  External Reset
      8. 8.3.8  ON_OFF_CONFIG
      9. 8.3.9  Output Voltage Adjustment
      10. 8.3.10 Calibration
      11. 8.3.11 Analog Front End (AFE)
      12. 8.3.12 Voltage Sense Filtering
      13. 8.3.13 DPWM Engine
      14. 8.3.14 Rail/Power Stage Configuration
      15. 8.3.15 DPWM Phase Synchronization
      16. 8.3.16 Output Current Measurement
      17. 8.3.17 Current Sense Input Filtering
      18. 8.3.18 Over-Current Detection
      19. 8.3.19 Input Voltage Monitoring
      20. 8.3.20 Input UV Lockout
      21. 8.3.21 Temperature Monitoring
      22. 8.3.22 Auxiliary ADC Input Monitoring
      23. 8.3.23 Soft Start, Soft Stop Ramp Sequence
      24. 8.3.24 Non-Volatile Memory Error Correction Coding
      25. 8.3.25 Data Logging
    4. 8.4 Device Functional Modes
      1. 8.4.1 4-Bit VID Mode
      2. 8.4.2 6-Bit VID Mode
      3. 8.4.3 8-Bit VID Mode
      4. 8.4.4 Current Foldback Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Automatic System Identification (Auto-ID)
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Digital Compensator
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Voltage applied at V33D to DGND –0.3 to 3.8 V
Voltage applied at V33A to AGND –0.3 to 3.8 V
Voltage applied to any terminal(2) –0.3 to 3.8 V
Maximum junction temperature (TJ) 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range -55 150 °C

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V Supply voltage during operation, V33D, V33DIO, V33A 3 3.3 3.6 V
TJ Operating junction temperature range –55 125 °C

7.4 Thermal Information

THERMAL METRIC(1) UCD9244-EP UNIT
QFN
64 TERMINAL
θJA Junction-to-ambient thermal resistance(2) 24.6 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 10
θJB Junction-to-board thermal resistance(4) 4.2
ψJT Junction-to-top characterization parameter(5) 0.2
ψJB Junction-to-board characterization parameter(6) 4.1
θJCbot Junction-to-case (bottom) thermal resistance(7) 1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS MIN NOM MAX UNIT
SUPPLY CURRENT
IV33A Supply current V33A = 3.3 V 8 15 mA
IV33DIO V33DIO = 3.3 V 42 55 mA
IV33 Total V33 supply current, V33A = V33DIO = 3.3 V 54 80 mA
IV33DIO V33D = 3.3 V storing configuration parameters in flash memory 52 65 mA
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS
V33 3.3-V linear regulator Emitter of NPN transistor 3.25 3.3 3.6 V
V33FB 3.3-V linear regulator feedback 4 4.6 V
IV33FB Series pass base drive VIN = 12 V 0.2 0.4 8 mA
Beta Series NPN pass device 40
EXTERNALLY SUPPLIED 3.3 V POWER
V33D, V33DIO1, V33DIO2 Digital 3.3-V power TJ = 25°C 3.0 3.6 V
V33A Analog 3.3-V power TJ = 25°C 3.0 3.6 V
ERROR AMPLIFIER INPUTS EAPn, EANn
VCM Common mode voltage each terminal 0 1.8 V
VERROR Internal error Voltage range AFE_GAIN field of CLA_GAINS = 1X(1) –256 248 mV
EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_Gains = 8X 1 mV
REA Input Impedance Ground reference, TJ = 25°C 1.5 MΩ
IOFFSET Input offset current 1-kΩ source impedance,TJ = 25°C –5 5 µA
Vref 10-bit DAC
Vref Reference Voltage Setpoint 0 1.7 V
Vrefres Reference Voltage Resolution 1.56 mV
ANALOG INPUTS CS1A, CS2A, CS3A, CS4A,VinMon, Temp1, Temp2, Temp3, Temp4, Addr0, Addr1
VADC_RANGE Measurement range for voltage monitoring Inputs: VinMon, Temp1, Temp2, Temp3, Temp4, CS1A, CS2A, CS3A, CS4A 0 2.6 V
Voffset input offset voltage –27 27 mV
VOC_THRS Over-current comparator threshold voltage range(2) Inputs: CS1A, CS2A, CS3A, CS4A 0.032 2 V
VOC_RES Over-current comparator threshold voltage range Inputs: CS, 1A, CS2A, CS3A, CS4A 31.25 mV
Tempinternal Int. temperature sense accuracy Over range from 0°C to 100°C –15 15 °C
INL ADC integral nonlinearity TJ = -40°C to 125°C –2.5 2.5 mV
Ilkg Input leakage current 3V applied to terminal 100 nA
RIN Input impedance Ground reference 8 MΩ
CIN Current Sense Input capacitance 10 pF
(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.
(2) Can be disabled by setting to '0'

7.6 Electrical Characteristics (Continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DIGITAL INPUTS/OUTPUTS
VOL Low-level output voltage IOL = 6 mA(1), V33DIO = 3 V Dgnd +0.3 V
VOH High-level output voltage IOH = -6 mA(2), V33DIO = 3 V V33DIO
–0.6V		 V
VIH High-level input voltage V33DIO = 3V 2.1 3.6 V
VIL Low-level input voltage V33DIO = 3.5 V 1.4 V
SYSTEM PERFORMANCE
VRESET Voltage where device comes out of reset V33D terminal 2.3 2.4 V
tRESET Pulse width needed for reset nRESET terminal 2 µs
VRefAcc Setpoint Reference Accuracy Vref commanded to be 1V, at 25°C AFEgain = 4,
1V input to EAP/N measured at output of the EADC(3)		 –10 10 mV
Setpoint Reference Accuracy over temperature –55°C to 125°C –40 40 mV
VDiffOffset Differential offset between gain settings AFEgain = 4 compared to
AFEgain = 1, 2, or 8		 –4 4 mV
tDelay Digital Compensator Delay 240 240 + 1 switching cycle ns
FSW Switching Frequency 15.260 2000 kHz
Accuracy –5% 5%
Duty Max and Min Duty Cycle 0% 100%
V33Slew Minimum V33 slew rate V33 slew rate between 2.3V and 2.9V,
TJ = -40°C to 125°C		 0.25 V/ms
tretention Retention of configuration parameters(6) TJ = 25 °C 100 Years
Write_Cycles Number of nonvolatile erase/write cycles TJ = 25 °C 20 K cycles
RateVID Max VID message rate All rails configured to accept VID messages(5) 1 msg/msec
All rails configured to accept 6-bit VID messages(5) 4
All rails configured to accept 8-bit VID messages(4) 4
(1) The maximum IOL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(2) The maximum IOH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
(3) With default device calibration. PMBus calibration can be used to improve the regulation tolerance.
(4) VID message rate on PMBus interface.
(5) VID message rate on each interface. Measured over a 1.0 msec interval.
(6) The data retention specification is based on accelerated stress testing at 170°C for 420 hours and using an Arrhenius model with activation energy of 0.6 eV.

7.7 ADC Monitoring Intervals And Response Times

The ADC operates in a continuous conversion sequence that measures each rail's output voltage and output current, plus six other variables (input voltage, internal temperature, and four external temperature sensors). The length of the sequence is determined by the number of output rails (NumRails) configured for use. The time to complete the monitoring sampling sequence is give by the formula: tADC_SEQ = tADC × (2 × NumRAILS + 6)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tADC ADC single-sample time 3.84 µs
tADC_SEQ ADC sequencer interval Min = 2 × 1 Rail + 6 = 8 samples
Max = 2 × 4 Rails + 6 = 14 samples		 30.72 53.76 µs

The most recent ADC conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The monitoring operates asynchronously to the ADC, at intervals shown in the table below.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tVout Output voltage monitoring interval 200 µs
tIout Output current monitoring interval 200×NRails µs
tVin Input voltage monitoring interval 1 ms
tTEMP Temperature monitoring interval 100 ms
tAUXADC Auxiliary ADC monitoring interval 100 ms

Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC sequence interval. Once a fault condition is detected, some additional time is required to determine the correct action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following table lists the worse-case fault response times.

PARAMETER TEST CONDITIONS TYP MAX
no VID		 MAX
/w VID(3)		 UNIT
tOVF, tUVF Over-/under-voltage fault response time during normal operation Normal regulation, no PMBus activity,
4 stages enabled		 250 800 µs
tOVF, tUVF Over-/under-voltage fault response time, during data logging During data logging to nonvolatile memory(1) 800 1000 µs
tOVF, tUVF Over-/under-voltage fault response time, when tracking or sequencing enable During tracking and soft-start ramp. 400 µs
tOCF, tUCF Over-/under-current fault response time during normal operation Normal regulation, no PMBus activity,
4 stages enabled 75% to 125% current step(2)		 100 +
(600 × NRails)		 5000 µs
tOCF, tUCF Over-/under-current fault response time, during data logging During data logging to nonvolatile memory 75% to 125% current step 600 +
(600 × NRails)		 5000 µs
tOTF Over-temperature fault response time Temperature rise of 10°C/sec, at OT threshold 1.60 sec
t3-State Time to tristate the PWM output after a shutdown is initiated DRIVER_CONFIG = 0x01 5.5 µs
(1) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can be up to 10 ms.
(2) Because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a combination of the time constant (τ) from Table 6, the recent measurement history, and how much the measured value exceeds the over-current limit.
(3) Controller receiving VID commands at a rate of 4000 msg/sec.

7.8 Hardware Fault Detection Latency

The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.

PARAMETER TEST CONDITIONS MAX TIME UNIT
tFAULT Time to disable DPWM output base on active FAULT terminal signal High level on FAULT terminal 18 µs
tCLF Time to disable the DPWM A output based on internal analog comparator Step change in CS voltage from 0V to 2.5V 4 Switch Cycles

7.9 PMBus/SMBus/I2C

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus are shown below.

SMBus_tim_slvsc86.gifFigure 1. I2C/SMBus/PMBus Timing In Extended Mode Diagram

7.10 I2C/SMBus/PMBus Timing Requirements

TJ = –55°C to 125°C, 3V < V33 < 3.6V, typical values at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMB SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz
fI2C I C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz
t(BUF) Bus free time between start and stop 5 µs
t(HD:STA) Hold time after (repeated) start 0.3 µs
t(SU:STA) Repeated start setup time 0.3 µs
t(SU:STO) Stop setup time 0.3 µs
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 55 ns
t(TIMEOUT) Error signal/detect See (1) 35 ms
t(LOW) Clock low period 0.55 µs
t(HIGH) Clock high period See (2) 0.3 50 µs
t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms
tFALL Clock/data fall time Rise time tRISE = VILMAX – 0.15) to (VIHMIN + 0.15),
TJ = -40°C to 125°C		 1000 ns
tRISE Clock/data rise time Fall time tFALL = 0.9 V33 to (VILMAX – 0.15),
TJ = -40°C to 125°C		 1000 ns
(1) The UCD9244 times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH) , max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9244 that is in progress.
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

7.11 Typical Characteristics

soft_start_graph_slvsc86.gifFigure 2. Soft-Start Ramp
soft_stop_graph_slvsc86.gifFigure 3. Soft-Stop Ramp