SLVSHK0 December   2025 UCD91160

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Linearity Parameters
    7. 5.7 POR and BOR
    8. 5.8 Low Frequency Crystal/Clock
    9. 5.9 Flash Memory Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 TI Sequencer Studio Software
      2. 6.3.2 PMBUS Interface
      3. 6.3.3 PMBUS Security
    4. 6.4 Device Functional Modes
      1. 6.4.1 Black Box First Fault Logging
      2. 6.4.2 PMBus Address Selection
      3. 6.4.3 Brownout
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.5 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Vin(ADC) Analog input voltage range(1)Applies to all ADC analog input pins0VDDV
VR+Positive ADC reference voltageVR+ sourced from VDDVDDV

Ts

ADC sample time per channel

250

ns

FS

ADC sampling frequency (per channel)

10

ksps

I(ADC)

Operating supply current into VDD terminal

VR+ = VDD1.5(2)mA
CS/HADC sample-and-hold capacitance3.3pF
RinADC input resistance0.5kΩ
ENOBEffective number of bitsExternal reference12.312.5bit
Internal reference, VR+ = 2.5V9.910.8
SNRSignal-to-noise ratioExternal reference (3)78dB
Internal reference, VR+ = 2.5V66
PSRRDCPower supply rejection ratio, DCExternal reference (3), VDD = VDD(min) to VDD(max)62dB
VDD = VDD(min) to VDD(max)
Internal reference, VR+ = 2.5V 		53
PSRRACPower supply rejection ratio, ACExternal reference (3), ΔVDD = 0.1V at 1kHz61dB
ΔVDD = 0.1V at 1kHz
Internal reference, VR+ = 2.5V 		52
(1) The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results.
(2) The internal reference (VREF) supply current is not included in current consumption parameter I(ADC).
(3) All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin