SLUSFA7 July   2025 UCC57142 , UCC57148

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable/Fault (EN/FLT)
      3. 6.3.3 Driver Stage
      4. 6.3.4 Over Current (OC) Protection
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 VDD Undervoltage Lockout
          2. 7.2.1.2.2 Power Dissipation
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Consideration
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DBV|6
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.6 Switching Characteristics

VDD = 15 V, 1-µF capacitor from VDD to COM, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR Output Rise Time CL=1.8 nF, 10% to 90%, Vin = 0 to 3.3 V 8 18 ns
tF Output Fall Time CL=1.8 nF, 90% to 10%, Vin = 0 to 3.3 V 14 32 ns
tD2 Propagation Delay – Input falling to output falling CL=1.8 nF, from 1 V falling on Vin to 90% of output fall, Vin=0 - 3.3 V, Fsw=500 kHz, 50% duty cycle 28 50 ns
tD1 Propagation Delay – Input rising to output rising CL=1.8 nF, from 2 V rising on Vin to 10% of output rise, Vin=0 - 3.3 V, Fsw=500 kHz, 50% duty cycle 26 50 ns
tPD_DIS DIS Response Delay CL=1.8 nF, from 1 V falling on EN to 90% of output fall, EN=0 - 3.3 V 27 45 ns
tPWD Pulse Width Distortion Input Pulse Width = 100 ns, 500 kHz
|tD2_1 – tD1_1|		 -10 10 ns
(1) Switching parameters are not tested in production.