The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC53x0 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC53x0 device, and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is measured on the bench with no load connected to the OUT or OUTH and OUTL pins at a given VCC1, VCC2, switching frequency, and ambient temperature. In this example, VCC1 is 3.3V and VCC2 is 15 V. The current on each power supply, with PWM switching from 0 V to 3.3 V at 10 kHz, is measured to be ICC1 = 1.67 mA and ICC2 = 1.11 mA. Therefore, use Equation 5 to calculate PGDQ.
The second component is the switching operation loss, PGDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 6 to calculate the total dynamic loss from load switching, PGSW.
So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated in Equation 7.
QG represents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change with different testing conditions. The UCC5320S gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss will be dissipated inside the UCC5320S. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4.3 A/4.4 A, however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
In this design example, all the predicted source and sink currents are less than 4.3 A and 4.4 A, therefore, use Equation 9 to estimate the UCC53x0 gate-driver loss.
Case 2 - Nonlinear Pull-Up/Down Resistor:
For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based on this discussion.
Use Equation 11 to calculate the total gate-driver loss dissipated in the UCC53x0 gate driver, PGD.