ZHCSGC2F June   2017  – January 2019 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1. 3.1 功能框图(S、E 和 M 版本)
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Function
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications for D Package
    7. 7.7  Insulation Specifications for DWV Package
    8. 7.8  Safety-Related Certifications For D Package
    9. 7.9  Safety-Related Certifications For DWV Package
    10. 7.10 Safety Limiting Values
    11. 7.11 Electrical Characteristics
    12. 7.12 Switching Characteristics
    13. 7.13 Insulation Characteristics Curves
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 8.1.1 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supply
      2. 9.3.2 Input Stage
      3. 9.3.3 Output Stage
      4. 9.3.4 Protection Features
        1. 9.3.4.1 Undervoltage Lockout (UVLO)
        2. 9.3.4.2 Active Pulldown
        3. 9.3.4.3 Short-Circuit Clamping
        4. 9.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 9.4 Device Functional Modes
      1. 9.4.1 ESD Structure
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing IN+ and IN– Input Filter
        2. 10.2.2.2 Gate-Driver Output Resistor
        3. 10.2.2.3 Estimate Gate-Driver Power Loss
        4. 10.2.2.4 Estimating Junction Temperature
      3. 10.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 10.2.3.1 Selecting a VCC1 Capacitor
        2. 10.2.3.2 Selecting a VCC2 Capacitor
        3. 10.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 10.2.4 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 认证
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 社区资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Undervoltage Lockout (UVLO)

UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2 and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO) at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected output low, regardless of the input pins (IN+ and IN–) as shown in Table 4. The VCC UVLO protection has a hysteresis feature (Vhys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise; this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly. Figure 55 shows the UVLO functions.

Table 2. UCC53x0 VCC1 UVLO Logic

CONDITION INPUTS OUTPUTS
IN+ IN– OUTH OUT, OUTL
VCC1 – GND1 < VIT+(UVLO1) during device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L
VCC1 – GND1 < VIT–(UVLO1) after device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L

Table 3. UCC53x0 VCC2 UVLO Logic

CONDITION INPUTS OUTPUTS
IN+ IN– OUTH OUT, OUTL
VCC2 – VEE2 < VIT+(UVLO2) during device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L
VCC2 – VEE2 < VIT–(UVLO2) after device start-up H L Hi-Z L
L H Hi-Z L
H H Hi-Z L
L L Hi-Z L

When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. Figure 55 shows this delay.

UCC5310 UCC5320 UCC5350 UCC5390 iso53xxd-illustration-of-UVLO-functions.gifFigure 55. UVLO Functions