SLUSEX2A September   2025  – September 2025 UCC27734 , UCC27735

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable Function (UCC277x5 Only)
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 6.3.7 HS Node dV/dt
      8. 6.3.8 Split Grounds (COM and VSS)
      9. 6.3.9 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC2773x Power Losses
        8. 7.2.2.8 Application Example Schematic Note
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.6 Dynamic Electrical Characteristics

At VDD=VHB=15V, COM=VHS=0, all voltages are with respect to COM, no load on LO and HO, –40°C<TJ< +150°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
PROPAGATION DELAYS
tDLFF VLI falling to VLO falling CLOAD = 0 pF, from VINL of LI to 90% of LO falling 32 49 ns
tDHFF VHI falling to VHO falling CLOAD = 0 pF,  from VINL of HI to 90% of HO falling 32 49 ns
tDLRR VLI rising to VLO rising CLOAD = 0 pF, from VINH of LI to 10% of LO rising 32 49 ns
tDHRR VHI rising to VHO rising CLOAD = 0 pF, from VINH of HI to 10% of HO rising 32 49 ns
tDLFF_SD VEN falling to VLO falling (UCC27735 only) CLOAD = 0 pF, from VENL of EN to 90% of LO falling 32 49 ns
tDHFF_SD VEN falling to VHO falling (UCC27735 only) CLOAD = 0 pF,  from VENL of EN to 90% of HO falling 32 49 ns
tDLRR_EN VEN rising to VLO rising (UCC27735 only) CLOAD = 0 pF, from VENH of EN to 10% of LO rising 32 49 ns
tDHRR_EN VEN rising to VHO rising (UCC27735 only) CLOAD = 0 pF, from VENH of EN to 10% of HO rising 32 49 ns
DELAY MATCHING
tMON HI OFF, LI ON TJ = 25°C, |tDHFF – tDLRR| 5 ns
tMON HI OFF, LI ON TJ = -40°C to 150°C, |tDHFF – tDLRR| 6 ns
tMOFF LI OFF, HI ON TJ = 25°C, |tDLFF – tDHRR| 5 ns
tMOFF LI OFF, HI ON TJ = -40°C to 150°C, |tDLFF – tDHRR| 6 ns
OUTPUT RISE AND FALL TIME
tR_LO LO rise time CLOAD = 1000 pF, from 10% to 90% 7 ns
tR_HO HO rise time CLOAD = 1000 pF, from 10% to 90% 7 ns
tF_LO LO fall time CLOAD = 1000 pF, from 90% to 10% 6 ns
tF_HO HO fall time CLOAD = 1000 pF, from 90% to 10% 6 ns
MISCELLANEOUS
tON Minimum HI/LI ON pulse that changes output state 0 V to 5 V input signal on HI & LI pins, CLOAD = 1nF 11 20 ns
tOFF Minimum HI/LI OFF pulse that changes output state 5 V to 0 V input signal on HI & LI pins, CLOAD = 1nF 11 20 ns