ZHCSKO8C June   2021  – January 2022 UCC27614

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Undervoltage Lockout
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Device Functional Modes
  8. 8  Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input-to-Output Configuration
          2. 8.2.1.2.2 Input Threshold Type
          3. 8.2.1.2.3 VDD Bias Supply Voltage
          4. 8.2.1.2.4 Peak Source and Sink Currents
          5. 8.2.1.2.5 Enable and Disable Function
          6. 8.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 8.2.1.2.7 Power Dissipation
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Consideration
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.6 Switching Characteristics

Unless otherwise noted, VDD = VEN = 12 V, IN- = GND, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, No load on the output. Typical condition specifications are at 25°C (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRRise timeCLOAD = 1.8 nF, 20% to 80%, VIN = 0 V to 3.3 V

4.5

6ns
tFFall timeCLOAD = 1.8 nF, 90% to 10%, VIN = 0 V to 3.3 V

4

5.5ns
tD1Turnon propagation delayCLOAD = 1.8 nF, VIN_H of the input rise to 10% of output rise, VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C17.527ns
tD2Turn-off propagation delayCLOAD = 1.8 nF, VIN_L of the input fall to 90% of output fall, VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C17.527ns
tPD_ENEnable propagation delayCLOAD = 1.8 nF, VEN_H of the enable rise to 10% of output rise, VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C17.527ns
tPD_DISDisable propagation delayCLOAD = 1.8 nF, VEN_L of the enable fall to 90% of output fall, VIN = 0 V to 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C17.527ns
tVDD+_OUTVDD UVLO ON delayVDD = 0 V to 4.5 V in 100 ns. Measured delay from VDD = 4.5 V to 10% of OUT3.26µs
tVDD-_OUTVDD UVLO OFF delayVDD = 4.5 V to 3.4 V in 100 ns. Measured delay from VDD = 3.4 V to 90% of OUT7.5us
tPWminMinimum input pulse width that passes to the outputCLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw = 500 kHz, Vo > 1.5 V

9

15ns
(1) Switching parameters are not tested in production.