ZHCSHQ7B February   2018  – April 2024 UCC21222-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Minimum Pulses
    2. 6.2 Propagation Delay and Pulse Width Distortion
    3. 6.3 Rising and Falling Time
    4. 6.4 Input and Disable Response Time
    5. 6.5 Programmable Dead Time
    6. 6.6 Power-Up UVLO Delay to OUTPUT
    7. 6.7 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 7.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Designing INA/INB Input Filter
        3. 8.2.2.3 Select Dead Time Resistor and Capacitor
        4. 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Estimating Gate Driver Power Loss
        7. 8.2.2.7 Estimating Junction Temperature
        8. 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.8.1 Selecting a VCCI Capacitor
          2. 8.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.8.3 Select a VDDB Capacitor
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 说明

UCC21222-Q1 器件是具有可编程死区时间和宽温度范围的隔离式双通道栅极驱动器。该器件在极端温度条件下表现出一致的性能和稳定性。该器件采用 4A 峰值拉电流和 6A 峰值灌电流来驱动功率 MOSFET、IGBT 和 GaN 晶体管。

UCC21222-Q1 器件可配置为两个低侧驱动器、两个高侧驱动器或一个半桥驱动器。该器件的 5ns 延迟匹配性能允许并联两个输出，能够在重负载条件下将驱动强度提高一倍，而无内部击穿风险。

输入侧通过一个 3.0kVRMS 隔离层与两个输出驱动器相隔离，其共模瞬态抗扰度 (CMTI) 的最小值为 125V/ns。

可通过电阻器进行编程的死区时间帮助您调整系统限制的死区时间，从而提高效率并防止输出重叠。其他保护特性包括：当 DIS 设置为高电平时，通过禁用功能同时关闭两路输出；集成的抗尖峰滤波器可抑制短于 5ns 的输入瞬变；以及在输入和输出引脚上对高达 -2V 的尖峰进行 200ns 的负电压处理。所有电源都有 UVLO 保护。

器件信息
器件型号 封装(1) 封装尺寸（标称值）
UCC21222-Q1 D (SOIC 16) 9.9mm × 3.91mm
(1) 有关所有可选封装，请参阅节 13。
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