ZHCSTF0B February   2019  – October 2023 TUSB2E22

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Parametric Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 2.0
      2. 8.3.2 eUSB2
      3. 8.3.3 Cross MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1 Repeater Mode
      2. 8.4.2 Power Down Mode
      3. 8.4.3 CROSS
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Dual Port System Implementation
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up Reset
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Example YCG Layout For Application With No Cross MUX Function.
      3. 9.4.3 Example RZA Layout For Application With No Cross MUX Function
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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6.7 Timing Requirements

MIN NOM MAX UNIT
RESET TIMING
t_VDD1V8_RAMP Ramp time for VDD1V8 to reach minimum 1.62 V 2 ms
t_VDD3V3_RAMP Ramp time for VDD3V3 to reach minimum 3.0 V 2 ms
t_su_CROSS Setup time for CROSS sampled at the de-assertion of RESETB 0 ms
t_hd_CROSS Hold time for CROSS sampled at the de-assertion of RESETB 3 ms
t_aRESETB duration for RESETB to be asserted low to complete reset while powered 10 us
t_RH_READY Time for eUSB2 interface to be ready after RESETB is de-asserted or (VDD1V8 and VDD3V3) reach minimum recommended voltages, whichever is later  3 ms