SLLSFB2 April   2020 TUSB1146

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematics
  4. 4 Revision History
  5. 5 TUSB1146 Pin Configuration and Functions
    1.     TUSB1146 Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  Control I/O DC Electrical Characteristics
    7. 6.7  USB and DP Electrical Characteristics
    8. 6.8  DCI Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 VOD modes
        1. 8.4.5.1 Linearity VOD
        2. 8.4.5.2 Limited VOD
      6. 8.4.6 Transmit Equalization
      7. 8.4.7 USB3.1 Modes
      8. 8.4.8 Downstream Facing Port Adaptive Equalization
        1. 8.4.8.1 Fast Adaptive Equalization in I2C Mode
        2. 8.4.8.2 Full Adaptive Equalization
    5. 8.5 Programming
      1. 8.5.1 Transition between Modes
      2. 8.5.2 Pseudocode Examples
        1. 8.5.2.1 Fast AEQ with linear redriver mode
        2. 8.5.2.2 Fast AEQ with limited redriver mode
        3. 8.5.2.3 Full AEQ with linear redriver mode
        4. 8.5.2.4 Full AEQ with limited redriver mode
      3. 8.5.3 TUSB1146 I2C Address Options
      4. 8.5.4 TUSB1146 I2C Slave Behavior
    6. 8.6 Register Maps
      1. 8.6.1 TUSB1146 Registers
        1. 8.6.1.1  General_1 Register (Offset = 0xA) [reset = 0x1]
          1. Table 13. General_1 Register Field Descriptions
        2. 8.6.1.2  DCI_TXEQ_CTRL Register (Offset = 0xB) [reset = 0x6C]
          1. Table 14. DCI_TXEQ_CTRL Register Field Descriptions
        3. 8.6.1.3  DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
          1. Table 15. DP01EQ_SEL Register Field Descriptions
        4. 8.6.1.4  DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
          1. Table 16. DP23EQ_SEL Register Field Descriptions
        5. 8.6.1.5  DisplayPort_1 Register (Offset = 0x12) [reset = 0x0]
          1. Table 17. DisplayPort_1 Register Field Descriptions
        6. 8.6.1.6  DisplayPort_2 Register (Offset = 0x13) [reset = 0x0]
          1. Table 18. DisplayPort_2 Register Field Descriptions
        7. 8.6.1.7  AEQ_CONTROL1 Register (Offset = 0x1C) [reset = 0xF0]
          1. Table 19. AEQ_CONTROL1 Register Field Descriptions
        8. 8.6.1.8  AEQ_CONTROL2 Register (Offset = 0x1D) [reset = 0x20]
          1. Table 20. AEQ_CONTROL2 Register Field Descriptions
        9. 8.6.1.9  AEQ_LONG Register (Offset = 0x1E) [reset = 0x77]
          1. Table 21. AEQ_LONG Register Field Descriptions
        10. 8.6.1.10 USBC_EQ Register (Offset = 0x20) [reset = 0x0]
          1. Table 22. USBC_EQ Register Field Descriptions
        11. 8.6.1.11 SS_EQ Register (Offset = 0x21) [reset = 0x0]
          1. Table 23. SS_EQ Register Field Descriptions
        12. 8.6.1.12 USB3_MISC Register (Offset = 0x22) [reset = 0x44]
          1. Table 24. USB3_MISC Register Field Descriptions
        13. 8.6.1.13 USB_STATUS Register (Offset = 0x24) [reset = 0x41]
          1. Table 25. USB_STATUS Register Field Descriptions
        14. 8.6.1.14 VOD_CTRL Register (Offset = 0x32) [reset = 0x40]
          1. Table 26. VOD_CTRL Register Field Descriptions
        15. 8.6.1.15 AEQ_STATUS Register (Offset = 0x3B) [reset = 0x0]
          1. Table 27. AEQ_STATUS Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C receptacle) Configuration
        2. 9.2.2.2 USB Downstream Facing Port (USB-C receptacle to USB Host) Configuration
          1. 9.2.2.2.1 Fixed Equalization
          2. 9.2.2.2.2 Fast Adaptive Equalization
          3. 9.2.2.2.3 Full Adaptive Equalization
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6.7 USB and DP Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB Gen 2 Differential Receiver (RX1p/n, RX2p/n, SSTXp/n)
V(RX-DIFF-PP) Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 1200 mVpp
V(RX-DC-CM) Common-mode voltage bias in the receiver (DC) 0 V
VRX_CM-INST Max Instantaneous RX DC common mode voltage change under all operating conditions (OFF to ON, Disabled to USB, etc…) Measured at non-TUSB1146 side of AC coupling capacitor with  200-kΩ load. -200   500 mV
R(RX-DIFF-DC) Differential input impedance (DC) Present after a GEN2 device is detected on TXP/TXN 72 90 120 Ω
R(RX-CM-DC) Receiver DC common mode impedance Present after a GEN2 device is detected on TXP/TXN 18 30 Ω
Z(RX-HIGH-IMP-DC-POS) Common-mode input impedance with termination disabled (DC) Present when no GEN2 device is detected on TXP/TXN. Measured over the range of 0-500mV with respect to GND. 25 kΩ
V(SIGNAL-DET-DIFF-PP) Input differential peak-to-peak signal detect assert level At 10 Gbps, no input loss, PRBS7 pattern 80 mV
V(RX-IDLE-DET-DIFF-PP) Input differential peak-to-peak signal detect de-assert Level At 10 Gbps, no input loss, PRBS7 pattern 60 mV
V(RX-LFPS-DET-DIFF-PP) Low frequency periodic signaling (LFPS) detect threshold Below the minimum is squelched 100 300 mV
V(RX-CM-AC-P) Peak RX AC common-mode voltage Measured at package pin 150 mV
C(RX) RX input capacitance to GND At 5 GHz; 0.88 1 pF
RL(RX-DIFF) Differential return Loss 50 MHz – 1.25 GHz at 90 Ω; –19 dB
5 GHz at 90 Ω; –10 dB
RL(RX-CM) Common-mode return loss 50 MHz – 5 GHz at 90 Ω; –10 dB
EQ_SSTX15 SSTX Receiver equalization at 5 GHz FLIPSEL = 0; SSEQ_SEL = 15; 11.5 dB
EQ_RX15 RX1 Receiver equalization at 5 GHz FLIPSEL = 0; EQ1_SEL = 15; 11.0 dB
CAC-USB1 Required external AC capacitor on SSTX 75 265 nF
CAC-USB2 Optional external AC capacitor on RX1 and RX2. 297 363 nF
USB Gen 2 Differential Transmitter (TX1p/n, TX2p/n, SSRXp/n)
VTX(DIFF-PP) Transmitter dynamic differential voltage swing range. 1200 mVpp
VTX(RCV-DETECT) Amount of voltage change allowed during receiver detection 600 mV
VTX-CM-INST-ONOFF Max Instantaneous TX DC common mode voltage change under operating condition:  OFF to ON, ON to OFF, during Rx.Detect; Disconnect to U0, U2/U3 to U0. Measured single-ended at non-TUSB1146 side of AC coupling capacitor with  200-kΩ load. -500   800 mV
VTX(CM-IDLE-DELTA) Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS –300 600 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0 1 V
VTX(CM-AC-PP-ACTIVE) Tx AC common-mode voltage active Max mismatch from Txp + Txn for both time and amplitude 100 mVpp
VTX(IDLE-DIFF-AC-PP) AC electrical idle differential peak-to-peak output voltage At package pins 0 10 mV
VTX(CM-DC-ACTIVE-IDLE-DELTA) Absolute DC common-mode voltage between U1 and U0 At package pin 200 mV
RTX(DIFF) Differential impedance of the driver 80 90 120 Ω
RTX(CM) Common-mode impedance of the driver Measured with respect to AC ground over
0–500 mV		 18 30 Ω
VSSRX-LIMITED-VODL0 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L0 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 800 mVpp
VSSRX-LIMITED-VODL1 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L1 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 900 mVpp
VSSRX-LIMITED-VODL2 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L2 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 1000 mVpp
VSSRX-LIMITED-VODL3 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L3 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 1100 mVpp
VSSRX-DE-RATIO0 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b00; USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 25 -1.5 dB
VSSRX-DE-RATIO1 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 25 -2.1 dB
VSSRX-DE-RATIO2 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 25 -3.2 dB
VSSRX-DE-RATIO3 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 25 -3.8 dB
VSSRX-PRESH-RATIO0 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b00;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 26 1.5 dB
VSSRX-PRESH-RATIO1 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 26 2.0 dB
VSSRX-PRESH-RATIO2 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 26 2.3 dB
VSSRX-PRESH-RATIO3 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 26 2.8 dB
ITX(SHORT) TX short circuit current TX± shorted to GND 40 mA
CTX(PARASITIC) TX input capacitance for return loss At package pins, at 5 GHz 0.9 1.25 pF
RLTX(DIFF) Differential return loss 50 MHz – 1.25 GHz at 90 Ω -30 dB
5 GHz at 90 Ω -21 dB
RLTX(CM) Common-mode return loss 50 MHz – 5 GHz at 90 Ω -10 dB
CTX-AC(COUPLING) External required AC coupling capacitor 75 265 nF
AC Characteristics
Crosstalk Differential crosstalk between TX and RX signal pairs at 5 GHz; EQ = 0; –30 dB
CPLF-LINRL0 Low-frequency 1-dB compression point at LINR_L0 setting.  At 100 MHz, 200 mVpp < VID < 1200 mVpp 600 mVpp
CPHF-LINRL0 High-frequency 1-dB compression point at LINR_L0 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp 550 mVpp
CPLF-LINRL1 Low-frequency 1-dB compression point at LINR_L1 setting.   At 100 MHz, 200 mVpp < VID < 1200 mVpp 700 mVpp
CPHF-LINRL1 High-frequency 1-dB compression point at LINR_L1 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp 650 mVpp
CPLF-LINRL2 Low-frequency 1-dB compression point at LINR_L2 setting.   At 100 MHz, 200 mVpp < VID < 1200 mVpp 800 mVpp
CPHF-LINRL2 High-frequency 1-dB compression point at LINR_L2 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp 750 mVpp
CPLF-LINRL3 Low-frequency 1-dB compression point at LINR_L3 setting.   At 100 MHz, 200 mVpp < VID < 1200 mVpp 900 mVpp
CPHF-LINRL3 High-frequency 1-dB compression point at LINR_L3 setting.   At 5 GHz, 200 mVpp < VID < 1200 mVpp 830 mVpp
fLF Low frequency cutoff 200 mVPP< VID < 1200 mVPP 20 50 kHz
tTX_DJ_USB TX output deterministic residual jitter when operating in USB mode. Optimual EQ setting; 12-in prechannel (SDD21 = -11.2dB); 1.6-in post channel (SDD21 = -1.8dB); PRBS7; 10 Gbps .07 UI
tTX_DJ_DP TX output deterministic residual jitter when operating in DP mode. Optimual EQ setting;12-in prechannel (SDD21 = -11.2dB); 1.6-in post channel (SDD21 = -1.8dB); PRBS7; 8.1 Gbps .04 UI
DisplayPort Receiver (DP[3:0]p/n)
VID(PP) Peak-to-peak input differential dynamic voltage range 1400 V
VIC Input common mode voltage 0 1.75 2 V
VRX_CM-INST Max Instantaneous RX DC common mode voltage change under all operating conditions (OFF to ON, Disabled to 4DP, etc…) Measured single-ended at non-TUSB1146 side of AC coupling capacitor with  50-Ω load. -300 500 mV
dR Data rate 10 Gbps
R(ti) Input termination resistance 75 90 110 Ω
C(AC) External required AC coupling capacitance 75 265 nF
EQ_DP15 DP0 Receiver equalization at 4.05 GHz FLIPSEL = 0; DP0EQ_SEL = 15; 12 dB
EQ_DP15 DP0 Receiver equalization at 5 GHz FLIPSEL = 0; DP0EQ_SEL = 15; 12.3 dB
DisplayPort Transmitter (TX1p/n, TX2p/n, RX1p/n, RX2p/n)
VTX-CM-INST Max Instantaneous TX DC common mode voltage change under all operating conditions (Disabled to 4DP, etc…) Measured at non-TUSB1146 side of AC coupling capacitor with  50-Ω load. -500   1000 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0 1 V
AUXp or AUXn and SBU1 or SBU2
RON Output ON resistance VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn		 2 5.5 10 Ω
ΔRON ON resistance mismatch within pair VCC = 3.3 V; VI = 0 to 0.4 V for AUXP;
VI = 2.7 V to 3.6 V for AUXN		 2.5 Ω
RON(FLAT) ON resistance flatness (RON max – RON min) measured at identical VCC and temperature VCC = 3.3 V; VI = 0 to 0.4 V for AUXp;
VI = 2.7 V to 3.6 V for AUXn		 2 Ω
V(AUXP_DC_CM) AUX Channel DC common mode voltage for AUXp and SBU1. VCC = 3.3 V; 0 0.4 V
V(AUXN_DC_CM) AUX Channel DC common mode voltage for AUXn and SBU2 VCC = 3.3 V; 2.7 3.6 V
C(AUX_ON) ON-state capacitance VCC = 3.3 V; CTL1 = 1; VI = 0 V
or 3.3 V		 4 7 pF
C(AUX_OFF) OFF-state capacitance VCC = 3.3 V; CTL1 = 0; VI = 0 V
or 3.3 V		 3 6 pF