ZHCSMM6 April   2022 TUSB1142

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
    1.     说明
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.2 2:1 MUX Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1142 I2C Address Options
      3. 7.5.3 TUSB1142 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 TUSB1142 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
  9. 9 Typical Application
  10. 10Design Requirements
  11. 11Detailed Design Procedure
    1. 11.1 USB SSTX Receiver Configuration
    2. 11.2 USB CRX1/2 Receiver Configuration
      1. 11.2.1 Fixed Equalization
      2. 11.2.2 Full Adaptive Equalization
      3. 11.2.3 Fast Adaptive Equalization
  12. 12Application Curves
  13. 13Power Supply Recommendations
  14. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  15. 15Device and Documentation Support
    1. 15.1 接收文档更新通知
    2. 15.2 支持资源
    3. 15.3 Trademarks
    4. 15.4 Electrostatic Discharge Caution
    5. 15.5 术语表
  16. 16Mechanical, Packaging, and Orderable Information

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5.8 Timing Requirements

MIN NOM MAX UNIT
USB3.1
tIDLEEntry Delay from U0 to electrical idle Refer to Figure 6-4. 10 ns
tIDELExit_U1 U1 exit time: break in electrical idle to the transmission of LFPS Refer to Figure 6-4. 1 ns
tIDLEExit_U2U3 U2/U3 exit time: break in electrical idle to transmission of LFPS Refer to Figure 6-4. 10 µs
tRXDET_INTVL RX detect interval while in Disconnect 12 ms
tIDLEExit_DISC Disconnect Exit Time 10 µs
tExit_SHTDN Shutdown Exit Time 0.75 ms
tAEQ_FULL_DONE Maximum time to obtain optimum EQ setting when operating in Full AEQ mode. 400 µs
tAEQ_FAST_DONE Maximum time to determine appropriate EQ setting when operating in Fast AEQ mode. 60 µs
tDIFF_DLY Differential Propagation Delay Refer to Figure 6-3. 300 ps
tR, tF Output Rise/Fall time 20%-80% of differential voltage measured 1.7 inch from the output pin; Refer to Figure 6-5. 30 ps
tRF_MM Output Rise/Fall time mismatch 20%-80% of differential voltage measured 1.7 inch from the output pin 2.6 ps
Power-up
tEN_LOW EN pin held low after supply reaches VCC(min) Refer to Figure 6-1 5 ms
tCFG_SU CFG(1) high Refer to Figure 6-1 250 µs
tCFG_HD CFG(1) high Refer to Figure 6-1 500 µs
(1) Following pins comprise CFG pins:  MODE, CEQ[1:0], SSEQ[1:0], EQCFG, AEQCFG