ZHCS904I May   2012  – March 2017 TRF7964A

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID - Reader and Writer
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver - Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver - Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI - Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter - Analog Section
    8. 6.8  Transmitter - Digital Section
    9. 6.9  Transmitter - External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7964A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7964A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7964A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
        1. 6.13.1.1  Idle (0x00)
        2. 6.13.1.2  Software Initialization (0x03)
        3. 6.13.1.3  Reset FIFO (0x0F)
        4. 6.13.1.4  Transmission With CRC (0x11)
        5. 6.13.1.5  Transmission Without CRC (0x10)
        6. 6.13.1.6  Delayed Transmission With CRC (0x13)
        7. 6.13.1.7  Delayed Transmission Without CRC (0x12)
        8. 6.13.1.8  Transmit Next Time Slot (0x14)
        9. 6.13.1.9  Block Receiver (0x16)
        10. 6.13.1.10 Enable Receiver (0x17)
        11. 6.13.1.11 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        12. 6.13.1.12 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    14. 6.14 Register Description
      1. 6.14.1 Register Preset
      2. 6.14.2 Register Overview
      3. 6.14.3 Detailed Register Description
        1. 6.14.3.1 Main Configuration Registers
          1. 6.14.3.1.1 Chip Status Control Register (0x00)
          2. 6.14.3.1.2 ISO Control Register (0x01)
        2. 6.14.3.2 Control Registers - Sublevel Configuration Registers
          1. 6.14.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.14.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.14.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.14.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.14.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.14.3.2.7  RX Wait Time Register (0x08)
          8. 6.14.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.14.3.2.9  RX Special Setting Register (0x0A)
          10. 6.14.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.14.3.3 Status Registers
          1. 6.14.3.3.1 IRQ Status Register (0x0C)
          2. 6.14.3.3.2 Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.14.3.3.3 RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.14.3.3.4 Special Functions Register (0x10)
          5. 6.14.3.3.5 Special Functions Register (0x11)
          6. 6.14.3.3.6 Adjustable FIFO IRQ Levels Register (0x14)
        4. 6.14.3.4 Test Registers
          1. 6.14.3.4.1 Test Register (0x1A)
          2. 6.14.3.4.2 Test Register (0x1B)
        5. 6.14.3.5 FIFO Control Registers
          1. 6.14.3.5.1 FIFO Status Register (0x1C)
          2. 6.14.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7964A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和下一步
    2. 8.2 器件命名规则
    3. 8.3 工具与软件
    4. 8.4 文档支持
    5. 8.5 社区资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Absolute Maximum Ratings(1) (2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Input voltage range –0.3 6 V
IIN Maximum current VIN 150 mA
TJ Maximum operating virtual junction temperature Any condition 140 °C
Continuous operation, long-term reliability(3) 125 °C
TSTG Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to substrate ground terminal VSS.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V
Machine model (MM) ±200 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN Operating input voltage 2.7 5 5.5 V
TA Operating ambient temperature –40 25 110 °C
TJ Operating virtual junction temperature –40 25 125 °C
VIL Input voltage, logic low I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.2 × VDD_I/O V
VIH Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.8 × VDD_I/O V

5.4 Electrical Characteristics

TYP operating conditions are TA = 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage 0.2 × VDD_I/O V
VOH High-level output voltage 0.8 × VDD_I/O V
IPD1 Supply current in power down mode 1 All building blocks disabled, including supply-voltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0) 0.5 5 µA
IPD2 Supply current in power down mode 2 (sleep mode) The SYS_CLK generator and VDD_X remain active to support external circuitry; measured after 100-ms settling time (EN = 0, EN2 = 1) 120 200 µA
ISTBY Supply current in stand-by mode Oscillator running, supply-voltage regulators in low-consumption mode (EN = 1, EN2 = x) 1.9 3.5 mA
ION1 Supply current without antenna driver current Oscillator, regulators, RX and AGC active, TX is off 10.5 14 mA
ION2 Supply current, TX (half power) Oscillator, regulators, RX and AGC and TX active, POUT = 100 mW 70 78 mA
ION3 Supply current, TX (full power) Oscillator, regulators, RX and AGC and TX active, POUT = 200 mW 130 150 mA
VPOR Power-on-reset voltage Input voltage at VIN 1.4 2 2.6 V
VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V
VDD_A Regulated output voltage for analog circuitry (pin 1) VIN = 5 V 3.1 3.4 3.8 V
VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 V
IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA
RRFOUT Antenna driver output resistance (3) Half-power mode, VIN = 2.7 V to 5.5 V 8 12 Ω
Full-power mode, VIN = 2.7 V to 5.5 V 4 6
RRFIN RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ
VRF_INmax Maximum RF input voltage at RX_IN1 and RX_IN2 VRF_INmax should not exceed VIN 3.5 Vpp
VRF_INmin Minimum RF input voltage at RX_IN1 and RX_IN2 (input sensitivity)(1) fSUBCARRIER = 424 kHz 1.4 2.5 mVpp
fSUBCARRIER = 848 kHz 2.1 3
fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz
fC Carrier frequency Defined by external crystal 13.56 MHz
tCRYSTAL Crystal run-in time Time until oscillator stable bit is set (register 0x0F)(2) 3 ms
fD_CLKmax Maximum DATA_CLK frequency(1) Depends on capacitive load on the I/O lines, TI recommends 2 MHz(1) 2 4 10 MHz
ROUT Output resistance I/O_0 to I/O_7 500 800 Ω
RSYS_CLK Output resistance RSYS_CLK 200 400 Ω
(1) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.
(2) Depends on the crystal parameters and components
(3) Antenna driver output resistance

5.5 Thermal Resistance Characteristics

PACKAGE θJC θJA(1) POWER RATING(2)
TA ≤ 25°C TA ≤ 85°C
RHB (32 pin) 31°C/W 36.4°C/W 2.7 W 1.1 W
(1) This data was taken using the JEDEC standard high-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.

5.6 Switching Characteristics

TYP operating conditions are TA = 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLO/HI DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle Depends on capacitive load on the I/O lines(1) 250 62.5 50 ns
tSTE,LEAD Slave select lead time, slave select low to clock 200 ns
tSTE,LAG Slave select lag time, last clock to slave select high 200 ns
tSTE,DIS Slave select disable time, slave select rising edge to next slave select falling edge 300 ns
tSU,SI MOSI input data setup time 15 ns
tHD,SI MOSI input data hold time 15 ns
tSU,SO MISO input data setup time 15 ns
tHD,SO MISO input data hold time 15 ns
tVALID,SO MISO output data valid time DATA_CLK edge to MISO valid,
CL ≤ 30 pF		 30 50 75 ns
(1) TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used).