SLVSI55A December   2025  – December 2025 TPSM8F7420 , TPSM8F7620

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC)
      3. 7.3.3  Device Configuration Pin (MSEL)
      4. 7.3.4  Multiphase Output Configuration
      5. 7.3.5  Enable and Adjustable UVLO
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Device Synchronization (SYNC)
        1. 7.3.7.1 Clock Locking
      8. 7.3.8  Adjustable Output Voltage (FB)
      9. 7.3.9  Control Loop Compensation (COMP)
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power-Good Output Voltage Monitoring
      12. 7.3.12 Output Discharge
      13. 7.3.13 Soft-Start (SS)
      14. 7.3.14 Overcurrent Protection (OCP)
      15. 7.3.15 Temperature Output
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Module Operating Area
        3. 8.2.2.3  Choosing the Switching Frequency
        4. 8.2.2.4  Setting the Output Voltage
        5. 8.2.2.5  Integrated Inductor Considerations
        6. 8.2.2.6  Input Capacitor Selection
        7. 8.2.2.7  Soft-Start Capacitor
        8. 8.2.2.8  VCC and BOOT Capacitors
        9. 8.2.2.9  Output Capacitor Selection
        10. 8.2.2.10 Compensation Selection
      3. 8.2.3 Application Curves
    3. 8.3 2-PH Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves 2-PH
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
  • APG|112
散热焊盘机械数据 (封装 | 引脚)

7.3.11 Power-Good Output Voltage Monitoring

The PG pin of the TPSM8F7x20 resembles a standard open-drain power-good function. There are three major differences between the PG function and the normal power-good function seen in most regulators:

  • A delay has been added for release of reset. See Table 7-5.
  • PG output signals a fault (pulls the output to ground) while the part is disabled.
  • PG continues to operate with input voltage as low as 1.2V. Below this input voltage, PG output can be high impedance.

A 10kΩ or greater pullup resistor from PG to VCC or external voltage source is required for proper PG signaling.

There are a total of four power-good pins on the TPSM8F7x20. If the device is configured to have four outputs, indicating the 1+1+1+1 configuration, then each VOUTx have a corresponding PGx. However, for configurations with less than four outputs, only the primary channel's PG pin is used. For example, in a 4+0 configuration, PG1 is the only power-good pin that is used and the rest can be left floating.

TPSM8F7420 TPSM8F7620 PG Static Voltage Thresholds Figure 7-5 PG Static Voltage Thresholds
TPSM8F7420 TPSM8F7620 PG Timing Diagram (Excludes OV Events) Figure 7-6 PG Timing Diagram (Excludes OV Events)
Table 7-5 Conditions that Cause PG to Signal a Fault (Pull Low)
PG FALLING CONDITIONS PG RISING CONDITIONS
FB below VPGTH-2 for longer than tPGOOD(F) FB above VPGTH-1
FB above VPGTH-3 for longer than tPGOOD(F) FB below VPGTH-4
Thermal Shutdown Junction temperature falls below TJ(SD)- TJ(HYS)
EN low tEN passes after EN becomes high
VIN below VINUVLO(F), but above VIN(PG_VALID) VIN above VINUVLO(R)

In addition to signaling a fault upon overvoltage detection (FB above VPGTH-3 for longer than tPGOOD(F)), the switch node is shut down and a small, approximately 1mA pulldown is applied to the SW node. Once the output overvoltage fault is removed (FB below VPGTH-4)) then switching resumes on the SW node.

The PG signal can be used for start-up sequencing of downstream regulators, or for fault protection and output monitoring.