ZHCSAO9A December   2012  – September 2015 TPS92690

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Current Regulators
      2. 7.3.2  Peak Current Mode Control
      3. 7.3.3  Switching Frequency and Synchronization
      4. 7.3.4  Current Sense and Current Limit
      5. 7.3.5  Average LED Current
      6. 7.3.6  Precision Reference (VREF)
      7. 7.3.7  Low-Level Analog Dimming
      8. 7.3.8  Soft-Start and Shutdown
      9. 7.3.9  VCC Regulator and Start-Up
      10. 7.3.10 Overvoltage Protection (OVP)
      11. 7.3.11 Input Undervoltage Lockout (UVLO)
      12. 7.3.12 PWM Dimming
      13. 7.3.13 Control Loop Compensation
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Inductor
      2. 8.1.2 LED Dynamic Resistance
      3. 8.1.3 Output Capacitor
      4. 8.1.4 Input Capacitor
      5. 8.1.5 MOSFET Selection
      6. 8.1.6 Recirculating Diode
    2. 8.2 Typical Applications
      1. 8.2.1 Basic Topology Schematics
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Operating Point
          2. 8.2.1.2.2  Switching Frequency
          3. 8.2.1.2.3  Average LED Current
          4. 8.2.1.2.4  Inductor Ripple Current
          5. 8.2.1.2.5  Output Capacitance
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Loop Compensation
          8. 8.2.1.2.8  Input Capacitance
          9. 8.2.1.2.9  NFET
          10. 8.2.1.2.10 Diode
          11. 8.2.1.2.11 Input UVLO
          12. 8.2.1.2.12 Output OVLO
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Simplified Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Operating Point
          2. 8.2.2.2.2  Switching Frequency
          3. 8.2.2.2.3  Average LED Current
          4. 8.2.2.2.4  Inductor Ripple Current
            1. 8.2.2.2.4.1 Minimum Inductor Value
            2. 8.2.2.2.4.2 Inductor Ripple Current
            3. 8.2.2.2.4.3 RMS Inductor Current
          5. 8.2.2.2.5  LED Ripple Current
            1. 8.2.2.2.5.1 Output Capacitor
            2. 8.2.2.2.5.2 Output Capacitor RMS Current
          6. 8.2.2.2.6  Peak Current Limit
          7. 8.2.2.2.7  Loop Compensation
            1. 8.2.2.2.7.1 Compensation Capacitor
            2. 8.2.2.2.7.2 RHP Zero
            3. 8.2.2.2.7.3 Output Capacitor Pole
          8. 8.2.2.2.8  Input Capacitance
          9. 8.2.2.2.9  NFET
            1. 8.2.2.2.9.1 Maximum Average NFET Current
            2. 8.2.2.2.9.2 RMS Transistor Current
          10. 8.2.2.2.10 Diode
            1. 8.2.2.2.10.1 Maximum Average Diode Current
          11. 8.2.2.2.11 Output OVLO
          12. 8.2.2.2.12 Input UVLO
          13. 8.2.2.2.13 Soft-Start
          14. 8.2.2.2.14 PWM Dimming Method
          15. 8.2.2.2.15 Analog Dimming Method
  9. 9 Power Supply Recommendations
    1. 9.1 Bench Supply Current Limit
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

All voltages are with respect to GND, –40°C < TJ = TA< 125°C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VIN –0.3 76 V
Input voltage nDIM, OVP –0.3 76 V
IS(2) –0.3 76
CSP, IADJ, SS/SD, ILIM –0.3 6
Output voltage VCC, GATE(3) –0.3 14 V
COMP, RT, VREF –0.3 6
Continuous input current IS –1 mA
GATE –1 1
SYNC 1
Output current VREF –1 mA
Operating junction temperature, TJ(4) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The IS pin can sustain –2 V for 100 ns without damage.
(3) the GATE pin can sustain –2.5 V for 100 ns. The VCC pin can sustain –2.5 V for 100 ns.
(4) Maximum junction temperature is internally limited.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 4.5 12 75 V
TJ Operating junction temperature –40 25 125 °C
VIADJ(max) Maximum operating IADJ voltage 0 5 V

6.4 Thermal Information

THERMAL METRIC(1) TPS92690 UNIT
PWP (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 39.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23.8 °C/W
RθJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 17.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C < TJ = TA < 125°C, VIN = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STARTUP REGULATOR (VCC)
VCCREG VCC regulation voltage ICC = 0 mA 6.35 6.9 7.45 V
ICCLIM VCC current limit VVCC = 0 V –20 –30 mA
IQ Quiescent current 2 3 mA
ISD Shutdown current VSS/SD = 0 V 45 65 μA
VCCUV VCC UVLO threshold VVCC rising 4.1 4.50 V
VVCC falling 3.61 4.01
VCCHYS VCC UVLO hysteresis 83 mV
REFERENCE VOLTAGE OUTPUT
VREF Reference voltage No load 2.4 2.45 2.5 V
ERROR AMPLIFIER
CSP input bias current –0.6 0 0.6 μA
COMP sink current 17.1 28.5 39.9 μA
COMP source current VIADJ = 5 V –12.6 –16.8 –21 μA
gM Transconductance VIADJ = 1 V, 0 V ≤ VCSP ≤ 0.8 V 33 μA/V
Transconductance bandwidth –6dB 1 MHz
IADJ pin input impedance 1 MΩ
VCSP Error amplifier reference voltage Precise value implied in offset VIADJ/10 V
Error amplifier input offset voltage VVCC = 4.5 V, 1 V ≤ VCOMP ≤ 1.4 V, TA = 25°C –1.5 0 1.5 mV
VVCC > 6 V, 1 V ≤ VCOMP ≤ 3 V, VIADJ ≤ 1.25 V, TA = 25°C –1.8 0 1.8
VVCC > 6 V, 1 V ≤ VCOMP ≤3 V, VIADJ > 1.25 V, TA = 25°C (% of ) –1.44 0 1.44 VCSP%
PWM COMPARATOR AND SLOPE COMPENSATION
DMAX Maximum duty cycle Internal oscillator only 90% 94.4%
IS to PWM offset voltage No slope added 950 1100 1250 mV
D = DMAX (maximum slope added) 125
IOFF IS source current No slope added –11.9 μA
IOFF + ISL D = DMAX (maximum slope added) –60 μA
CURRENT LIMIT
ILIM delay to output 60 100 ns
tON(min) Leading edge blanking time 200 300 ns
Current limit off-timer 38 μs
ILIM offset voltage D = 50% –19 –5.6 5 mV
LOW POWER SHUTDOWN AND SOFTSTART
VSD Shutdown threshold voltage VSS/SD falling 30 86 mV
VSDH Shutdown hysteresis 24 mV
ISS SS/SD current source VSS/SD > (VSD + VSDH) –10.8 μA
VSS/SD < VSD –1.1 μA
OSCILLATOR AND EXTERNAL SYNCHRONIZATION
ƒSW Switching frequency RRT = 121 kΩ 312 350 389 kHz
RRT = 100 kΩ 372 418 464
RRT = 84.5 kΩ 436 490 544
SYNC threshold voltage (falling edge triggers on-time) Rising 2.05 2.36 V
Falling 0.95 1.31
SYNC Clamp Voltage Positive 6.2 V
Negative –0.5
OVERVOLTAGE PROTECTION
OVP OVLO threshold Rising 1.23 1.282 V
Falling 1.144 1.19
OVP hysteresis source current OVP active (high) –14 –21.5 –28 μA
PWM DIMMING INPUT AND UVLO
nDIM/UVLO threshold Rising 1.23 1.285 V
Falling 1.14 1.19
nDIM hysteresis current –14 –21.6 –28 μA
GATE DRIVER
GATE sourcing resistance GATE = High 2.4 6 Ω
GATE sinking resistance GATE = Low 1 5 Ω
Peak GATE current Source –0.47 A
Sink 1.1 A
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 175 °C
TSD(hys) Thermal shutdown hysteresis 25 °C

6.6 Typical Characteristics

Unless otherwise noted, –40°C ≤ TA = TJ≤ 125°C, VVIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF
TPS92690 G000_lvsbk3.png
Figure 1. Boost Efficiency vs Input Voltage
TPS92690 G002_lvsbk3.png
Figure 3. Boost Line Regulation
TPS92690 G004_lvsbk3.png
Figure 5. 160-Hz Boost PWM Dimming
TPS92690 G006_lvsbk3.png
Figure 7. Switching Frequency vs Ambient Temperature
(RT = 100 kΩ)
TPS92690 G008_lvsbk3.png
Figure 9. Output Current vs Ambient Temperature
TPS92690 G001_lvsbk3.png
Figure 2. Boost Efficiency vs Input Voltage
TPS92690 G003_lvsbk3.png
Figure 4. Switching Frequency vs RT Resistance
TPS92690 G005_lvsbk3.png
Figure 6. IADJ Analog Dimming (RCS = 0.25 Ω)
TPS92690 G007_lvsbk3.png
Figure 8. Efficiency vs Ambient Temperature
TPS92690 G009_lvsbk3.png
Figure 10. VREF Voltage vs Ambient Temperature