ZHCSPL6 January   2022 TPS7H4003-SEP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjust UVLO
      7. 7.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 7.3.7.1 Internal Oscillator Mode
        2. 7.3.7.2 External Synchronization Mode
        3. 7.3.7.3 Primary-Secondary Operation Mode
      8. 7.3.8  Soft-Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Sequencing
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Turn-On Behavior
      15. 7.3.15 Slope Compensation
        1. 7.3.15.1 Slope Compensation Requirements
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Output Schottky Diode
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Soft-Start Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 8.2.2.8 Output Voltage Feedback Resistor Selection
          1. 8.2.2.8.1 Minimum Output Voltage
        9. 8.2.2.9 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.7.2 External Synchronization Mode

In external synchronization mode, a resistor is connected between the RT pin and GND corresponding to the external clock frequency as indicated in Equation 4 and Figure 7-4. During this mode of operation, the SYNC1 pin connects to the input clock and the SYNC2 pin must be connected to either GND or VIN depending on whether it is desired to invert the clock SYNC1 receives. When SYNC2 is connected to GND, the clock provided on SYNC1 is inverted. When SYNC2 is connected to VIN, the input clock signal on SYNC1 does not get inverted. As a result, external synchronization mode can be used to connect 2, 3, or 4 devices in parallel using an external clock (at any frequency between 100 kHz and 1 MHz) as long as the clocks used for each device are in the proper out of phase configuration. If no external clock signal is detected for 20 µs, then the TPS7H4003-SEP transitions to its internal clock and a switching frequency that is determined by the value of the RT resistor. If no external clock is available, then the primary-secondary operation mode can also be used to connect devices in parallel.