ZHCSEP4A January 2016 – February 2016 TPS7A85
The TPS7A85 is a high-current (4 A), low-noise (4.4 µVRMS), high accuracy (1%) low-dropout linear voltage regulator (LDO). These features make the device a robust solution to solve many challenging problems in generating a clean, accurate power supply.
The TPS7A85 has several features that make the device useful in a variety of applications. As detailed in the Functional Block Diagram section, these features include:
Overall, these features make the TPS7A85 the component of choice because of its versatility and ability to generate a supply for most applications.
NOTE:For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual resistance can vary significantly from the values listed.
The TPS7A85 includes a low-noise reference and error amplifier ensuring minimal noise during operation. The NR/SS capacitor (CNR/SS) and feed-forward capacitor (CFF) are the most effective way to reduce device noise. CNR/SS filters the noise from the reference and CFF filters the noise from the error amplifier. The noise contribution from the charge pump is minimal. The overall noise of the system at low output voltages can be reduced by using a bias rail because this rail provides more headroom for internal circuitry.
The high power-supply rejection ratio (PSRR) of the TPS7A85 ensures minimal coupling of input supply noise to the output. The PSRR performance primarily results from a high-bandwidth, high-gain error amplifier and an innovative circuit to boost the PSRR between 200 kHz and 1 MHz.
The combination of a low noise floor and high PSRR ensure that the device provides a clean supply to the application; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.
An internal feedback resistance network is provided, allowing the TPS7A85 output voltage to be programmed easily between 0.8 V to 3.95 V with a 50-mV step by tying the ANY-OUT pins to ground. Tying the ANY-OUT pins to SNS increases the resolution but limits the range of the output voltage because the effective value of R1 is decreased. The ANY-OUT network provides excellent accuracy across output voltage and temperature; see the Application and Implementation section for more details.
The device features a bias rail to enable low-input voltage, low-output (LILO) voltage operation by providing power to the internal circuitry of the device. The bias rail is required for operation with VIN < 1.4 V.
An internal power MUX supplies the greater of either the input voltage or the bias voltage to an internal charge pump to power the internal circuitry. Unlike other LDOs that have a bias supply, the TPS7A85 does not have a minimum bias voltage with respect to the input supply because an internal charge pump is used instead.
The internal charge pump multiples the output voltage of the power MUX by a factor of 4 to a maximum of typically 8 V; therefore, using a bias supply with VIN ≤ 2.2 V is recommended for optimal dc and ac performance. Sequencing requirements exist for when the bias rail is used; see the Sequencing Requirements section for more details.
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the feedback pin voltage falls below the PG threshold voltage (VIT(PG) + VHYS(PG), typically 89.3%), the PG pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG) (typically 91.3%), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external voltage detector device such as the TPS3702 is also recommended in applications where more accurate voltage monitoring or overvoltage monitoring is required.
The use of a feed-forward capacitor (CFF) can cause glitches on start-up, and the power-good circuit may not function normally below the minimum input supply range. For more details on the use of the power-good circuitry, see the Power-Good (PG) Operation section.
Soft-start refers to the ramp-up time of the output voltage during LDO turn-on after EN and UVLO exceed the respective threshold voltages. The noise-reduction capacitor (CNR/SS) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp time during turn-on. The start-up ramp is monotonic.
The majority of the ramp is linear; however, there is an offset voltage in the error amplifier that can cause a small initial jump in output voltage; see the Application and Implementation section on implementing a soft-start.
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased load impedance. Thermal shutdown can activate during a current limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended.
The foldback current limit crosses 0 A when VOUT < 0 V and prevents the device from turning on into a negatively-biased output. See the Negatively-Biased Output section for additional ways to ensure start-up when the TPS7A85 output is pulled below ground.
If VOUT > VIN + 0.3 V, then reverse current can flow from the output to the input. The reverse current can cause damage to the device; therefore, limit this reverse current to 10% of the rated output current of the device. See the Reverse Current Protection section for more details.
The enable pin for the TPS7A85 is active high. The output of the TPS7A85 is turned on when the enable pin voltage is greater than its rising voltage threshold (1.1 V, max), and the output of the TPS7A85 is turned off when the enable pin voltage is less than its falling voltage threshold (0.5 V, min). A voltage less than 0.5 V on the enable pin disables all internal circuits. At the next turn-on this voltage ensures a normal start-up waveform with in-rush control, provided there is enough time to discharge the output capacitance.
When the enable functionality is not desired, EN must be tied to VIN. However, when the enable functionality is desired, the enable voltage must come after VIN is above VUVLO1(IN) when a BIAS rail is used; see the Application and Implementation section for further details.
The TPS7A85 has an internal pulldown MOSFET that connects a resistance of several hundred ohms to ground when the device is disabled to actively discharge the output voltage when the device is disabled.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 10% of the device rated current for a short period of time; see the Reverse Current Protection section for more details.
The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (VIN and VBIAS, respectively) to prevent the device from turning on before VIN and VBIAS rise above the lockout voltage. The UVLO circuit also disables the output of the device when VIN or VBIAS fall below the lockout voltage.
The UVLO circuit responds quickly to glitches on VIN or VBIAS and attempts to disable the output of the device if either of these rails collapse. As a result of the fast response time of the input supply UVLO circuit, fast slew rate and short duration line transients well below the input supply UVLO falling threshold can cause momentary glitches during the edges of the transient; see the Application and Implementation section for more details.
The TPS7A85 contains a thermal shutdown protection circuit to disable the device when thermal junction temperature (TJ) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached until the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the device to exceed its operational specifications. Although the internal protection circuitry of the TPS7A85 is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A85 into thermal shutdown or above a junction temperature of 125°C reduces long-term reliability.
The TPS7A85 requires a bias voltage on the BIAS pin greater than or equal to 3.0 V if the high-current input supply voltage is between 1.1 V to 1.4 V. The bias voltage pin consumes 2.3 mA, typically.
If the input voltage is equal to or exceeds 1.4 V, no BIAS voltage is required. The TPS7A85 is powered from either the input supply or the BIAS supply, whichever is greater. For higher performance, a BIAS rail is recommended for VIN ≤ 2.2 V.
Shutting down the device reduces the ground current of the device to a maximum of 25 µA.