ZHCSEI2B January   2016  – June 2021 TPS7A84

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Low-Noise, High-PSRR Output
      2. 7.3.2  Integrated Resistance Network (ANY-OUT)
      3. 7.3.3  Bias Rail
      4. 7.3.4  Power-Good Function
      5. 7.3.5  Programmable Soft-Start
      6. 7.3.6  Internal Current Limit (ILIM)
      7. 7.3.7  Enable
      8. 7.3.8  Active Discharge Circuit
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 1.1 V ≤ VIN < 1.4 V
      2. 7.4.2 Operation with 1.4 V ≤ VIN ≤ 6.5 V
      3. 7.4.3 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 8.1.3  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      4. 8.1.4  Feed-Forward Capacitor (CFF)
      5. 8.1.5  Soft-Start and In-Rush Current
      6. 8.1.6  Optimizing Noise and PSRR
      7. 8.1.7  Charge Pump Noise
      8. 8.1.8  ANY-OUT Programmable Output Voltage
      9. 8.1.9  ANY-OUT Operation
      10. 8.1.10 Increasing ANY-OUT Resolution for LILO Conditions
      11. 8.1.11 Current Sharing
      12. 8.1.12 Adjustable Operation
      13. 8.1.13 Sequencing Requirements
        1. 8.1.13.1 Sequencing with a Power-Good DC-DC Converter Pin
        2. 8.1.13.2 Sequencing with a Microcontroller (MCU)
      14. 8.1.14 Power-Good Operation
      15. 8.1.15 Undervoltage Lockout (UVLO) Operation
      16. 8.1.16 Dropout Voltage (VDO)
      17. 8.1.17 Behavior when Transitioning from Dropout into Regulation
      18. 8.1.18 Load Transient Response
      19. 8.1.19 Negatively-Biased Output
      20. 8.1.20 Reverse Current Protection
      21. 8.1.21 Power Dissipation (PD)
      22. 8.1.22 Estimating Junction Temperature
      23. 8.1.23 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application for a 5.0-V Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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8.1.2 Input and Output Capacitor Requirements (CIN and COUT)

The TPS7A84 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. Using at least a 47-µF capacitor is highly recommended at the input to minimize input impedance. Place the input and output capacitors as near as practical to the respective input and output pins to minimize trace parasitics. If the trace inductance from the input supply to the TPS7A84 is high, a fast current transient can cause VIN to ring above the absolute maximum voltage rating and damage the device. This situation can be mitigated by additional input capacitors to dampen the ringing and to keep it below the device absolute maximum ratings.

A combination of multiple output capacitors boosts the high-frequency PSRR, as illustrated in several of the PSRR curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,
10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes PSRR for the frequency range of 400 kHz to 700 kHz, a typical range for dc-dc supply switching frequency. This 47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a voltage derating of approximately 60% to 80% at 5.0 V, so the addition of the two 10-µF capacitors ensures that the capacitance is at or above 22 µF.