SBVS163A June   2011  – May 2015 TPS7A3401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Enable Pin Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Operation
      2. 8.1.2 Transient Response
      3. 8.1.3 Post DC-DC Converter Filtering
      4. 8.1.4 Power for Precision Analog
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Recommendations
          1. 8.2.2.1.1 Input and Output Capacitor Requirements
          2. 8.2.2.1.2 Feed-Forward Capacitor Requirements
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
Voltage IN pin to GND pin –22 0.3 V
OUT pin to GND pin –22 0.3
OUT pin to IN pin –0.3 22
FB pin to GND pin –2 0.3
FB pin to IN pin –0.3 22
EN pin to IN pin –0.3 22
EN pin to GND pin –22 22
NR/SS pin to IN pin –0.3 22
NR/SS pin to GND pin –2 0.3
Current Peak output Internally limited
Temperature Operating virtual junction, TJ –40 125 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VIN Input supply voltage –20 –3 V
VEN Enable supply voltage 0 VIN V
VOUT Output voltage VREF –18 V
IOUT Output current 0 200 mA
TJ Operating junction temperature –40 125 °C
CIN Input capacitor 2.2 10 µF
COUT Output capacitor 2.2 10 µF
CFF Feed-forward capacitor 0 10 nF
R2 Lower feedback resistor 237 kΩ

6.4 Thermal Information

THERMAL METRIC(1) TPS7A3401 UNIT
DGN (HVSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 63.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 53 °C/W
RθJB Junction-to-board thermal resistance 37.4 °C/W
ψJT Junction-to-top characterization parameter 3.7 °C/W
ψJB Junction-to-board characterization parameter 37.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 13.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 µF, COUT = 2.2 µF, and the FB pin tied to OUT, unless otherwise noted.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage –20 –3 V
VREF Internal reference TJ = 25°C, VFB = VREF –1.202 –1.184 –1.166 V
VOUT Output voltage(2) |VIN| ≥ |VOUT(nom)| + 1 V –18 VREF V
Nominal accuracy TJ = 25°C, |VIN| = |VOUT(nom)| + 0.5 V –1.5 1.5 %VOUT
Overall accuracy |VOUT(nom)| + 1 V ≤ |VIN| ≤ 20 V
1 mA ≤ IOUT ≤ 200 mA		 –2.5 2.5 %VOUT
TPS7A3401 q_line_reg_bvs125.gif Line regulation TJ = 25°C, |VOUT(nom)| + 1 V ≤ |VIN| ≤ 20 V 0.14 %VOUT
TPS7A3401 q_load_reg_bvs125.gif Load regulation TJ = 25°C, 1 mA ≤ IOUT ≤ 200 mA 0.04 %VOUT
|VDO| Dropout voltage VIN = 95% VOUT(nom), IOUT = 100 mA 216 mV
VIN = 95% VOUT(nom), IOUT = 200 mA 500 800 mV
ICL Current limit VOUT = 90% VOUT(nom) 200 330 500 mA
IGND Ground current IOUT = 0 mA 55 100 μA
IOUT = 100 mA 950 μA
|ISHDN| Shutdown supply current VEN = 0.4 V 1 5 μA
VEN = –0.4 V 1 5 μA
IFB Feedback current(3) 14 100 nA
|IEN| Enable current VEN = |VIN| = |VOUT(nom)| + 1 V 0.48 1 μA
VIN = VEN = –20 V 0.51 1 μA
VIN = –20 V, VEN = 15 V 0.50 1 μA
VEN(+HI) Positive enable high-level voltage TJ = –40°C to 125°C 2 15 V
TJ = –40°C to 85°C 1.8 15
VEN(+LO) Positive enable low-level voltage 0 0.4 V
VEN(–HI) Negative enable high-level voltage VIN –2 V
VEN(–LO) Negative enable low-level voltage –0.4 0 V
Vn Output noise voltage VIN = –3 V, VOUT(nom) = VREF, COUT = 10 μF, BW = 10 Hz to 100 kHz 80 μVRMS
PSRR Power-supply rejection ratio VIN = –6.2 V, VOUT(nom) = –5 V,
COUT = 10 μF, f = 1 kHz		 50 dB
TSD Thermal shutdown temperature Shutdown, temperature increasing 170 °C
Reset, temperature decreasing 150
TJ Operating junction temperature –40 125 °C
(1) At operating conditions, VIN ≤ 0 V, VOUT(nom) ≤ VREF ≤ 0 V. At regulation, VIN ≤ VOUT(nom) – |VDO|. IOUT > 0 flows from OUT to IN.
(2) To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 μA is required.
(3) IFB > 0 flows into the device.

6.6 Typical Characteristics

At TJ = –40°C to 125°C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF, COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted.
TPS7A3401 tc_vfb-vin_bvs163.gif
Figure 1. Feedback Voltage vs Input Voltage
TPS7A3401 tc_ignd-vin_25c_bvs163.gif
Figure 3. Ground Current vs Input Voltage
TPS7A3401 tc_ignd-iout_bvs125.gif
Figure 5. Ground Current vs Output Current
TPS7A3401 tc_iq-vin_bvs163.gif
Figure 7. Quiescent Current vs Input Voltage
TPS7A3401 tc_vdo-iout_bvs125.gif
Figure 9. Dropout Voltage vs Output Current
TPS7A3401 tc_ilim-vin_bvs125.gif
Figure 11. Current Limit vs Input Voltage
TPS7A3401 tc_ven-tmp_bvs125.gif
Figure 13. Enable Threshold Voltage vs Temperature
TPS7A3401 tc_psrr_bvs163.gif
Figure 15. Power-Supply Rejection Ratio
TPS7A3401 tc_noise_bvs163.gif
Figure 17. Output Spectral Noise Density
TPS7A3401 tc_ifb-tmp_bvs125.gif
Figure 2. Feedback Current vs Temperature
TPS7A3401 tc_ignd-vin_100ma_bvs163.gif
Figure 4. Ground Current vs Input Voltage
TPS7A3401 tc_ien-ven_bvs163.gif
Figure 6. Enable Current vs Enable Voltage
TPS7A3401 tc_ishdn-vin_bvs163.gif
Figure 8. Shutdown Current vs Input Voltage
TPS7A3401 tc_vdo-tmp_bvs163.gif
Figure 10. Dropout Voltage vs Temperature
TPS7A3401 tc_ilim-tmp_bvs125.gif
Figure 12. Current Limit vs Temperature
TPS7A3401 tc_line_reg_bvs163.gif
Figure 14. Line Regulation
TPS7A3401 tc_load_reg_bvs125.gif
Figure 16. Load Regulation