ZHCSDK5B September   2014  – January 2017 TPS68470

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements - Data Transmission
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-Up Sequence and Modes
      2. 8.3.2  Clock Generation
        1. 8.3.2.1 Crystal Oscillator
        2. 8.3.2.2 Phase Locked Loop (PLL)
        3. 8.3.2.3 Spread Spectrum Modulator
        4. 8.3.2.4 Clock Drivers
      3. 8.3.3  GPIO and Interrupt Generation
        1. 8.3.3.1 I2C Daisy Chain
        2. 8.3.3.2 Programmable Interrupt Trigger
        3. 8.3.3.3 Internal Interrupt Signals
      4. 8.3.4  Sensor GPO Signals
      5. 8.3.5  Power-Up and Software Reset
      6. 8.3.6  Core Buck
        1. 8.3.6.1 Buck Converter Switching Frequency
        2. 8.3.6.2 Buck Converter Internal Current Limit and Short Detection
      7. 8.3.7  Low Dropout Voltage Regulators (LDOs)
        1. 8.3.7.1 LDO Output Capacitor Requirements
        2. 8.3.7.2 LDO Internal Current Limit and Short Detection
        3. 8.3.7.3 Dropout Voltage
      8. 8.3.8  WLED Boost Converter and WLED Drivers
        1. 8.3.8.1 WLED Driver Operation
        2. 8.3.8.2 WLED Modes
          1. 8.3.8.2.1 FLASH: MODE[1:0] = '00''
          2. 8.3.8.2.2 TORCH: MODE[1:0] = '01''
          3. 8.3.8.2.3 RED-EYE REDUCTION: MODE[1:0] = '10''
          4. 8.3.8.2.4 FOCUS ASSIST: MODE[1:0] = '11''
        3. 8.3.8.3 WLED Trigger Options
          1. 8.3.8.3.1 Level-Sensitive Flash Trigger (TRIG = 0)
            1. 8.3.8.3.1.1 Edge Trigger Flash (TRIG = 1)
        4. 8.3.8.4 Blanking (Tx-Mask) for Instantaneous Flash-Current Reduction
        5. 8.3.8.5 Voltage Mode
      9. 8.3.9  Indicator LED Operation
        1. 8.3.9.1 Retriggerable Pulse Extender
      10. 8.3.10 Safe Operation and Protection Features
        1. 8.3.10.1 LED Temperature Monitoring (Finger-Burn Protection)
        2. 8.3.10.2 LED Failure Modes (Open/Short Detection) and Overvoltage Protection
        3. 8.3.10.3 WLED Open Circuit Detection/Over Voltage Protection
        4. 8.3.10.4 LED Current Ramp-Up/Down
        5. 8.3.10.5 Short Circuit Protection
        6. 8.3.10.6 Hot Die Detection and Thermal Shutdown
      11. 8.3.11 WLED Boost Inductor Selection
      12. 8.3.12 I2C Bus Operation
        1. 8.3.12.1 Single Write to a Defined Location
        2. 8.3.12.2 Single Read From a Defined Location and Current Location
        3. 8.3.12.3 Sequential Read and Write
      13. 8.3.13 Subaddress Definition
        1. 8.3.13.1 I2C Device Address, Start and Stop Condition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with a Single Input Power Rail
      2. 8.4.2 Sequencing the Input Power Rails
    5. 8.5 Register Map
      1. 8.5.1  GSTAT Register (address = 0x01) [reset = 00000000]
      2. 8.5.2  VRSTAT Register (address = 0x02) [reset = -]
      3. 8.5.3  VRSHORT Register (address = 0x03) [reset = 00000000]
      4. 8.5.4  INTMASK Register (address = 0x04) [reset = 00000000]
      5. 8.5.5  VCOSPEED Register (address = 0x05) [reset = 00000000]
      6. 8.5.6  POSTDIV2 Register (address = 0x06) [reset = 00000000]
      7. 8.5.7  BOOSTDIV Register (address = 0x07) [reset = 00000000]
      8. 8.5.8  BUCKDIV Register (address = 0x08) [reset = 00000000]
      9. 8.5.9  PLLSWR Register (address = 0x09) [reset = 00000000]
      10. 8.5.10 XTALDIV Register (address = 0x0A) [reset = 00000000]
      11. 8.5.11 PLLDIV Register (address = 0x0B) [reset = 00000000]
      12. 8.5.12 POSTDIV Register (address = 0x0C) [reset = 00000000]
      13. 8.5.13 PLLCTL Register (address = 0x0D) [reset = 10000000]
      14. 8.5.14 PLLCTL2 Register (address = 0x0E) [reset = 00000000]
      15. 8.5.15 CLKCFG1 Register (address = 0x0F) [reset = 00000000]
      16. 8.5.16 CLKCFG2 Register (address = 0x10) [reset = 00000000]
      17. 8.5.17 GPCTL0A Register (address = 0x14) [reset = 00000001]
      18. 8.5.18 GPCTL0B Register (address = 0x15) [reset = 00001000]
      19. 8.5.19 GPCTL1A Register (address = 0x16) [reset = 00000001]
      20. 8.5.20 GPCTL1B Register (address = 0x17) [reset = 00001000]
      21. 8.5.21 GPCTL2A Register (address = 0x18) [reset = 00000001]
      22. 8.5.22 GPCTL2B Register (address = 0x19) [reset = 00001000]
      23. 8.5.23 GPCTL3A Register (address = 0x1A) [reset = 00000001]
      24. 8.5.24 GPCTL3B Register (address = 0x1B) [reset = 00001000]
      25. 8.5.25 GPCTL4A Register (address = 0x1C) [reset = 00000001]
      26. 8.5.26 GPCTL4B Register (address = 0x1D) [reset = 00001000]
      27. 8.5.27 GPCTL5A Register (address = 0x1E) [reset = 00000001]
      28. 8.5.28 GPCTL5B Register (address = 0x1F) [reset = 00001000]
      29. 8.5.29 GPCTL6A Register (address = 0x20) [reset = 00000001]
      30. 8.5.30 GPCTL6B Register (address = 0x21) [reset = 00001000]
      31. 8.5.31 SGPO Register (address = 0x22) [reset = 00000000]
      32. 8.5.32 PITCTL Register (address = 0x23) [reset = 00000000]
      33. 8.5.33 WAKECFG Register (address = 0x24) [reset = 00000000]
      34. 8.5.34 IOWAKESTAT Register (address = 0x25) [reset = 00000000]
      35. 8.5.35 GPDI Register (address = 0x26) [reset = 00000000]
      36. 8.5.36 GPDO Register (address = 0x27) [reset = 00000000]
      37. 8.5.37 ILEDCTL Register (address = 0x28) [reset = 00000000]
      38. 8.5.38 WLEDSTAT Register (address = 0x29) [reset = 00000000]
      39. 8.5.39 VWLEDILIM Register (address = 0x2A) [reset = 00001010]
      40. 8.5.40 VWLEDVAL Register (address = 0x2B) [reset = 00000000]
      41. 8.5.41 WLEDMAXRER Register (address = 0x2C) [reset = 00000000]
      42. 8.5.42 WLEDMAXT Register (address = 0x2D) [reset = 00000000]
      43. 8.5.43 WLEDMAXAF Register (address = 0x2E) [reset = 00000000]
      44. 8.5.44 WLEDMAXF Register (address = 0x2F) [reset = 00000000]
      45. 8.5.45 WLEDTO Register (address = 0x30) [reset = 00000000]
      46. 8.5.46 VWLEDCTL Register (address = 0x31) [reset = 00111000]
      47. 8.5.47 WLEDTIMER_MSB Register (address = 0x32) [reset = 00000000]
      48. 8.5.48 WLEDTIMER_LSB Register (address = 0x33) [reset = 00000000]
      49. 8.5.49 WLEDC1 Register (address = 0x34) [reset = 00000000]
      50. 8.5.50 WLEDC2 Register (address = 0x35) [reset = 00000000]
      51. 8.5.51 WLEDCTL Register (address = 0x36) [reset = 00000000]
      52. 8.5.52 VCMVAL Register (address = 0x3C) [reset = 00000000]
      53. 8.5.53 VAUX1VAL Register (address = 0x3D) [reset = 00000000]
      54. 8.5.54 VAUX2VAL Register (address = 0x3E) [reset = 00000000]
      55. 8.5.55 VIOVAL Register (address = 0x3F) [reset = 00110100]
      56. 8.5.56 VSIOVAL Register (address = 0x40) [reset = 00110100]
      57. 8.5.57 VAVAL Register (address = 0x41) [reset = 00000000]
      58. 8.5.58 VDVAL Register (address = 0x42) [reset = 00000000]
      59. 8.5.59 S_I2C_CTL Register (address = 0x43) [reset = 00000000]
      60. 8.5.60 VCMCTL Register (address = 0x44) [reset = 00000000]
      61. 8.5.61 VAUX1CTL Register (address = 0x45) [reset = 00000000]
      62. 8.5.62 VAUX2CTL Register (address = 0x46) [reset = 00000000]
      63. 8.5.63 VACTL Register (address = 0x47) [reset = 00000000]
      64. 8.5.64 VDCTL Register (address = 0x48) [reset = 00000100]
      65. 8.5.65 RESET Register (address = 0x50) [reset = N/A]
      66. 8.5.66 REVID Register (address = 0xFF) [reset = 00100000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Core Buck Design
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Output Capacitor
          3. 9.2.2.1.3 Input Capacitor
        2. 9.2.2.2 WLED Boost Design
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Input Capacitor
        3. 9.2.2.3 LDOs Capacitor Selection
        4. 9.2.2.4 LED Selection
        5. 9.2.2.5 Recommended External Components
      3. 9.2.3 Application Performance Graphs
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Voltage 3V3_VDD, 3V3_SUS –0.3 3.96 V
DRV_WLED1, DRV_WLED2 –0.3 7.0
WLED_SW, WLED_OUT –0.3 7.0
CORE_SW –0.3 7.0
I2C_ICA, I2C_ICB, SDA, SCL –0.3 3.96
GPIO0-6 –0.3 3.96
S_RESETN, S_ENABLE, S_IDLE, S_VSYNC, S_STROBE –0.3 3.96
RESET_IN –0.3 3.96
OSC_IN, OSC_OUT –0.3 3.96
HCLK_A, HCLK_B –0.3 3.96
PLL_COMP1, PLL_COMP2 –0.3 3.96
VCM_OUT, ANA_OUT, IO_OUT, S_IO_OUT, AUX1_OUT, AUX2_OUT –0.3 3.96
CORE_FB –0.3 3.96
WLED_NTC –0.3 3.96
ILEDA, ILEDB –0.3 3.96
PLL_VDD –0.3 3.96
Continuous power dissipation, PD 1.6 W
Operating junction temperature, TJ –30 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.

7.2 ESD Ratings

VALUE UNIT
V(ESD)(3) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.

7.3 Recommended Operating Conditions

over operating free-air temperature (unless otherwise noted)
MIN NOM MAX UNIT
Voltage 3V3_VDD, 3V3_SUS 2.97 3.3 3.63 V
DRV_WLED1, DRV_WLED2 Setting Dependent
WLED_SW, WLED_OUT Setting Dependent
CORE_SW Setting Dependent
I2C_ICA, I2C_ICB 3.3
SDA, SCL 1.8 3.3
GPIO0-6 3.3
S_RESETN, S_ENABLE, S_IDLE, S_VSYNC, S_STROBE 3.3
RESET_IN 3.3
OSC_IN, OSC_OUT 3.3
HCLK_A, HCLK_B 3.3
PLL_COMP1, PLL_COMP2 3.3
VCM_OUT, ANA_OUT, IO_OUT, S_IO_OUT, AUX1_OUT, AUX2_OUT 3.1
CORE_FB 1.95
WLED_NTC 3.3
ILEDA, ILEDB 3.3
PLL_VDD 3.3
Operating ambient temperature, TA 0 85 °C

7.4 Thermal Information

THERMAL METRIC(1) YFF (DSBGA)
56 PINS		 UNIT
RθJA Junction-to-ambient thermal resistance 39.8 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.2
RθJB Junction-to-board thermal resistance 6.6
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 6.5
RθJCbot Junction-to-case (bottom) thermal resistance n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Over recommended free-air temperature and over recommended input voltage (typical at an ambient temperature range of 27°C ) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE and UVLO
VI(3V3_VDD) Operating input voltage 2.97 3.3 3.63 V
VI(3V3_SUS) Operating input voltage 2.97 3.3 3.63 V
IQ(3V3_VDD) 3V3_VDD quiescent current In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_IO enabled and with no load,
LDO_PLL, LDO_ANA, LDO_S_IO, LDO_AUX1, LDO_VCM, CORE and WLED_OUT disabled and with no load
LDO_AUX2 disabled and with no load		 65 100 145 µA
In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_IO enabled and with no load,
LDO_PLL, LDO_ANA, LDO_S_IO, LDO_AUX1, LDO_VCM, CORE and WLED_OUT disabled and with no load
LDO_AUX2 enabled and with no load - LDO_AUX2 current comes from 3V3_SUS		 65 100 145 µA
In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_ANA, LDO_IO, LDO_S_IO, LDO_AUX1, LDO_VCM, CORE and WLED_OUT enabled (default voltage settings) and with no load, LDO_PLL disabled, CORE and WLED_OUT running on internal oscillator
LDO_AUX2 disabled and with no load		 5 mA
In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_IO enabled and with no load,
LDO_PLL enabled, BUCKDIV [3:0] set to 5.2 MHz, BOOSTDIV [4:0] set to 2 MHz, POSTDIV for HCLK_A and HCLK_B set to 18 MHz
LDO_ANA, LDO_S_IO, LDO_AUX1, LDO_VCM, CORE and WLED_OUT disabled and with no load
LDO_AUX2 disabled and with no load		 0.91 mA
IQ(3V3_SUS) 3V3_SUS quiescent current In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_AUX2 disabled and with no load 25 35 50 µA
In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_AUX2 enabled and with no load 70 102 130 µA
In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_ANA, LDO_IO, LDO_S_IO, LDO_AUX1, LDO_VCM, CORE and WLED_OUT enabled (default voltage settings) and with no load, LDO_PLL disabled, CORE and WLED_OUT running on internal oscillator
LDO_AUX2 disabled and with no load		 255 µA
In ACTIVE mode, VI(3V3_VDD) = VI(3V3_SUS) = 3.3 V, LDO_IO enabled and with no load,
LDO_PLL enabled, BUCKDIV [3:0] set to 5.2 MHz, BOOSTDIV [4:0] set to 2 MHz, POSTDIV for HCLK_A and HCLK_B set to 18 MHz
LDO_ANA, LDO_S_IO, LDO_AUX1, LDO_VCM, CORE and WLED_OUT disabled and with no load
LDO_AUX2 disabled and with no load		 1.367 mA
In SLEEP mode, VI(3V3_VDD) = 0 V, VI(3V3_SUS) = 3.3 V, LDO_AUX2 disabled and with no load 0.3 1.1 µA
In SLEEP mode, VI(3V3_VDD) = 0 V, VI(3V3_SUS) = 3.3 V, LDO_AUX2 enabled and with no load 75 100 125 µA
UVLO3V3_VDD Under voltage lockout threshold at 3V3_VDD pin VI(3V3_VDD) going up 2.6 2.75 2.85 V
VI(3V3_VDD) going down 2.55 2.65 2.75
Hysteresis 0.1
UVLO3V3_SUS Under voltage lockout threshold at 3V3_SUS pin VI(3V3_SUS) going up 2.6 2.75 2.85 V
VI(3V3_SUS) going down 2.55 2.65 2.75
Hysteresis 0.1
BOOST CONVERTER (WLED_OUT)
VI(3V3_VDD) Input Voltage 2.97 3.3 3.63 V
VO(WLED_OUT) Output voltage range Current regulation mode VIN 5.5 V
Voltage regulation mode 3.68 5.48 V
Internal feedback voltage accuracy Boost mode, PWM voltage regulation –2% 2%
VOVP Output overvoltage protection VO(WLED_OUT) rising 5.7 6.0 6.25 V
Output overvoltage protection hysteresis VO(WLED_OUT) falling 100 mV
tstart Start-up time 1 ms
DWLED_SW Minimum duty cycle 7.5%
RDS(ON) Switch MOSFET on-resistance VO(WLED_OUT) = Vgs = 3.6 V 40 mΩ
Rectifier MOSFET on-resistance 40 mΩ
ILK(WLED_SW) Switch MOSFET leakage VWLED_SW = 3.6 V, TA = 85°C 0.22 1.2 µA
ILIM Switch current limit ILIM[3:0] = ‘1010’ 4.0 A
Selectable range (1) 2.0 5.0
CIN External Input capacitor 4.7 µF
CLC External LC capacitance 10 20 26 µF
LLC External LC inductance 1.3 2.2 2.9 µH
LED DRIVER
IDRV_WLEDx Maximum operating current per driver Driver on 1 A
DRV_WLEDx current accuracy 0.4 V ≤ VDRV_WLEDx ≤ 2.0 V,
0 mA ≤ IDRV_WLEDx ≤ 300 mA		 –10% 10%
0.4 V ≤ VDRV_WLEDx ≤ 2.0 V,
300 mA ≤ IDRV_WLEDx ≤ 1000 mA		 –7.5% 7.5%
DRV_WLED1 and DRV_WLED2 current matching –10% 10%
IILEDx Indicator LEDx driver maximum operating current 16 mA
ILEDx current accuracy VILEDx = 1.0 V at IILEDx = 16 mA –10% 10%
VSENSE(DRV_WLEDx) DRV_WLEDx sense voltage IDRV_WLEDx = full-scale current 400 mV
IlLK(DRV_WLEDx) DRV_WLEDx input leakage current VDRV_WLEDx = 3.6 V, TA = 85°C 5 µA
IlLK(ILEDx) ILEDx input leakage current VILEDx = 0 V, TA = 85°C 1 µA
LED TEMPERATURE MONITORING
IO(WLED_NTC) Temperature sense current source Thermistor bias current 23.8 µA
TS resistance (warning temperature) LEDWARN bit = 1 0.92 1.05 1.19 V
TS resistance (hot temperature) LEDHOT bit = 1 0.29 0.35 0.4 V
BUCK CONVERTER (CORE)
VI(3V3_VDD) Input voltage 2.97 3.3 3.63 V
VO(CORE) Regulated DC output voltage 0 mA ≤ IO ≤ 500 mA, DVOLT[5:0] = 0x0D 1.15 1.2 1.25 V
Output voltage range Range selectable with 25-mV steps 0.9 1.2 1.95 V
RDS(ON) High-Side MOSFET on resistance VI(3V3_VDD) = V(GS) = 3.3 V, 100% Duty Cycle 180 mΩ
Low-Side MOSFET on resistance VI(3V3_VDD) = V(GS) = 3.3 V, 0% Duty Cycle 150 mΩ
VSHORT Output short detection comparator VO(CORE)< VSHORTfor greater than 10 ms 0.5 V
RDIS Discharge resistor for power down sequence Core Disabled 190 375 Ω
IO(CORE) Output operating current 500 mA
P-MOS current limit 1000 mA
fSW Clock frequency range 3 5.2 6 MHz
RFB Feedback input resistance 500 kΩ
tRamp VO(CORE) ramp up time Time to ramp from 5% to 95% of VOUT (VO(CORE)=1.2 V) ,no load, typical COUT 85 200 µs
CIN External input capacitor 4.7 µF
CLC External LC capacitance 2.35 4.7 6.11 µF
LLC External LC inductance 0.5 1.0 1.3 µH
LDO_ANA
VI(3V3_VDD) Input voltage 3.3 V
VO(ANA_OUT) Output voltage See (2) 0.875 2.8 3.1 V
Output DC accuracy VI(3V3_VDD) - VO(ANA_OUT) > 200 mV –2% 2%
Dropout voltage V3V3_VDD = 0.975 × VOUT(NOM), IOUT = 200 mA 100 150 mV
Load regulation 0 mA ≤ Iout ≤ 200 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 200 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 2.8 V, IOUT = 0.75*200 mA 50 56 dB
f = 10 kHz, VI = 3.3 V, VO = 2.8 V, IOUT = 0.75*200 mA 30 38
VSHORT Output short detection comparator VO(ANA_OUT)< VSHORTfor greater than 10ms 0.5 V
Tstart Startup time COUT = 1.0 µF, VO(ANA_OUT) from 0 V to 2.8 V 100 µs
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
LDO_VCM
VI(3V3_VDD) Input Voltage 3.3 V
VO(VCM_OUT) Output voltage See (2) 0.875 2.8 3.1 V
Output DC accuracy VI(3V3_VDD) - VO(VCM_OUT) > 200 mV –2% 2%
Dropout voltage V3V3_VDD = 0.975 x VOUT(NOM), IOUT = 500 mA 100 150 mV
Load regulation 0 mA ≤ Iout ≤ 500 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 500 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 2.8 V, IOUT = 0.75*500 mA 50 60 dB
f = 10 kHz, VI = 3.3 V, VO = 2.8 V, IOUT = 0.75*500 mA 30 40
VSHORT Output short detection comparator VO(VCM_OUT)< VSHORTfor greater than 10ms 0.5 V
Tstart Startup time COUT = 1.0 µF, Vout from 0 V to 2.8 V 100 µs
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
LDO_AUX1
VI(3V3_VDD) Input voltage 3.3 V
VO(AUX1_OUT) Output voltage See (2) 0.875 1.2 3.1 V
Output accuracy VI(3V3_VDD) - VO(AUX1_OUT) > 200 mV –2% 2%
Dropout voltage V3V3_VDD = 0.975 × VOUT(NOM), IOUT = 150 mA 100 150 mV
Load regulation 0 mA ≤ Iout ≤ 150 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 150 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 1.2 V, IOUT = 0.75*150 mA 50 56 dB
f = 10 kHz, VI = 3.3 V, VO = 1.2 V, IOUT = 0.75*150 mA 30 38 dB
VSHORT Output short detection comparator VO(AUX1_OUT)< VSHORTfor greater than 10 ms 0.5 V
Tstart Startup time COUT = 1.0 µF, Vout from 0 V to 1.2 V 100 µs
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
LDO_AUX2
VI(3V3_SUS) Input voltage 3.3 V
VO(AUX2_OUT) Output voltage See (2) 0.875 1.8 3.1 V
Output accuracy VI(3V3_SUS) - VO(AUX2_OUT) > 200 mV –2% 2%
Dropout voltage V3V3_SUS = 0.975 x VOUT(NOM),
IOUT = 50 mA		 100 150 mV
Load regulation 0 mA ≤ Iout ≤ 50 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 80 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 1.8 V, IOUT = 0.75*50 mA 50 53 dB
f = 10 kHz, VI = 3.3 V, VO = 1.8 V, IOUT = 0.75*50 mA 30 38 dB
VSHORT Output short detection comparator VO(AUX2_OUT)< VSHORTfor greater than 10 ms 0.5 V
Tstart Startup time COUT = 1.0 µF, Vout from 0 V to 1.8 V 100 µs
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
LDO_IO
VI(3V3_VDD) Input voltage 3.3 V
VO(IO_OUT) Output voltage See (2) and (3) 1.6 1.8 3.1 V
Output DC accuracy VI(3V3_VDD) - VO(IO_OUT) > 200 mV –2% 2%
Dropout voltage V3V3_VDD = 0.975 × VOUT(NOM), IOUT = 50 mA 100 150 mV
Load regulation 0 mA ≤ Iout ≤ 50 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 50 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 1.8 V, IOUT = 0.75*50 mA 50 56 dB
f = 10 kHz, VI = 3.3 V, VO = 1.8 V, IOUT = 0.75*50 mA 30 38 dB
VSHORT Output short detection comparator VO(IO_OUT)< VSHORTfor greater than 10 ms 0.5 V
Tstart Startup time COUT = 1.0 µF, Vout from 0 V to 1.8 V 100 µs
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
LDO_S_IO
VI(3V3_VDD) Input Voltage 3.3 V
VO(S_IO_OUT) Output voltage See (2) 0.875 1.8 3.1 V
Output DC accuracy VI(3V3_VDD) - VO(S_IO_OUT) > 200 mV –2% 2%
Dropout voltage V3V3_VDD = 0.975 x VOUT(NOM), IOUT = 150 mA 100 150 mV
Load regulation 0 mA ≤ Iout ≤ 150 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 150 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 1.8 V, IOUT = 0.75*150 mA 50 53 dB
f = 10 kHz, VI = 3.3 V, VO = 1.8 V, IOUT = 0.75*150 mA 30 38 dB
VSHORT Output short detection comparator VO(S_IO_OUT)< VSHORTfor greater than 10 ms 0.5 V
Tstart Startup time COUT = 1.0 µF, Vout from 0 V to 1.8 V 100 ms
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
LDO_PLL (For Internal Use Only)
VI(3V3_VDD) Input voltage 3.3 V
VO(PLL_VDD) Output voltage See (2) 2.55 2.7 2.75 V
Output DC accuracy VI(3V3_VDD) - VO(PLL_VDD) > 200 mV –2% 2%
Dropout voltage V3V3_VDD = 0.975 x VOUT(NOM), IOUT = 50 mA 150 200 mV
Load regulation 0 mA ≤ Iout ≤ 50 mA 15 mV
Line regulation VOUT(NOM) + 0.3 V ≤ V3V3_VDD ≤ 3.63 V,
IOUT = 10 mA		 5 mV
Imax Max output current 50 mA
PSRR Power supply rejection ratio f = 1 kHz, VI = 3.3 V, VO = 2.7 V, IOUT = 0.75*50 mA 50 57 dB
f = 10 kHz, VI = 3.3 V, VO = 2.7 V, IOUT = 0.75*50 mA 30 40 dB
VSHORT Output short detection comparator VO(PLL_VDD)< VSHORTfor greater than 10 ms 0.5 V
Tstart Startup time COUT = 1.0 µF, Vout from 0 V to 2.7 V 100 µs
RDIS Discharge resistor in power down 100 200 Ω
COUT Output capacitance 0.5 1.0 1.3 µF
CLOCK GENERATION
fXTAL External reference clock 3 24 27 MHz
tstart PLL start-up time With FL2000044 crystal to 0.1% accuracy of the target frequency 1 ms
XTAL ESR 50 150 Ω
fHCLK Output clock minimum programmable frequency 3.8 4 4.2 MHz
maximum programmable frequency 63.8 64 64.2 MHz
DHCLK HCLKx duty cycle driven by PLL output 45% 55%
trise HCLKx rise time Measured from 10% to 90%, DRV_STR_x[1:0] = 2 mA 2 5 ns
tfall HCLKx fall time Measured from 90% to 10%, DRV_STR_x[1:0] = 2 mA 2 5 ns
Ƭ HCLKx jitter 3σ cycle-to-cycle. Greater than 1000 cycles. Difference between two consecutive cycles 600 ps
Cload HCLKx load maximum load capacitance for frequencies between 4 MHz and 32 MHz 10 pF
maximum load capacitance for frequencies up to 64 MHz 5
VOH HCLKx output high voltage IOH = 8 mA 0.7*VS_IO_OUT V
VOL HCLKx output low voltage IOL = 8 mA 0.2*VS_IO_OUT V
THERMAL SHUTDOWN
WLED BOOST thermal shutdown Trip temperature 140 160 °C
Hysteresis 20
Core buck thermal shutdown Trip temperature 140 160 °C
Hysteresis 20
LDO thermal shutdown Trip temperature 140 160 °C
Hysteresis 20
OSCILLATOR (for digital core)
fosc Oscillator frequency 1.8 2 2.2 MHz
S_VSYNC
VIH Input high level 1.0 V
VIL Input low level 0.4 V
RPD (S_VSYNC) S_VSYNC internal pull-down Only present when VS_VSYNC is below VIL threshold 5 10 kΩ
I2C I/Os (SDA, SCL) (IO_OUT voltage)
ILK Input leakage current Clamped to GND or 3.3 V –1 1 µA
VIH Input high level 0.7*VIO_OUT V
VIL Input low level 0.3*VIO_OUT V
VOL(SDA) Output low level (SDA) IOL = 3 mA 0.2*VIO_OUT V
fSCL I2C clock frequency 400 kHz
GPIOs (GPIO0, GPIO1, GPIO2, GPIO3,GPIO4,GPIO5 and GPIO6)
VIH Input high level Configured as Input 1.2 V
VIL Input low level Configured as Input 0.4 V
ILK Input leakage current Configured as input, clamped to GND or 3.3 V –1 1 µA
VOH_PP Output high level for push-pull configuration VO(IO_OUT) = 1.8 V or VI(3V3_SUS) = 3.3 V, IOH = 8 mA 0.8*VDD V
VOL_PP Output low level for push-pull configuration VO(IO_OUT) = 1.8 V or VI(3V3_SUS) = 3.3 V, IOL = 8 mA 0.2*VDD V
VOL_OD Output low level for open-drain configuration VO(IO_OUT) = 1.8 V or VI(3V3_SUS) = 3.3 V, IOL = 8 mA 0.2*VDD V
ILK_OD Output leakage current for open-drain configuration VO(IO_OUT) = 1.8 V or VI(3V3_SUS) = 3.3 V 1 µA
RPU GPIOs pull-up resistance if enabled 50 kΩ
CIN Internal pin capacitance 3.19 3.21 pF
SENSOR PASS GATES (GPIO1 to SDA and GPIO2 to SCL)
RDS SDA and SCL to GPIO1 and GPIO2 daisy chain switch on resistance 25 Ω
LOGIC INPUTS (S_STROBE, I2C_ICA, I2C_ICB) (S_IO_OUT voltage dependent - 3.3-V Tolerant)
ILK Input leakage current (does not apply to S_STROBE) Clamped to GND or 3.3 V –1 1 µA
VIH Input high level 1.2 V
VIL Input low level 0.4 V
RPD (S_STROBE) S_STROBE pull-down 50 kΩ
CIN Input pin capacitance 1.257 5.57 pF
LOGIC OUTPUTS (S_RESETN, S_ENABLE, S_IDLE)
VOH Output high level IOH = 8 mA 0.8*VS_IO_OUT V
VOL Output low level IOL = 8 mA 0.2*VS_IO_OUT V
LOGIC I/Os (RESET_IN ) (3V3_SUS voltage)
ILK Input leakage current Clamped to GND or 3.3 V –1 1 µA
VIH Input high level 0.9 V
VIL Input low level 0.5 V
RPU RESET_IN pull-up resistance 50 kΩ
(1) Boost current limit is selectable from register VWLEDILIM with 4-bits
(2) All LDO output voltages are selectable through a specific voltage adjustment register xVAL bits xVOLT[6:0] and can be adjusted from 0.875 V up to 3.1 V with steps of 17.8 mV. Output voltage register setting xVOLT[6:0] values (dec) can be calculated with the below formula:
SPACE
SPACE xVOLT(DEC) = round[(V_out – 0.875 V)/0.0178 V]
SPACE
(3) LDO_IO should never be set below 1.6 V, otherwise I2C communication is not functional.

7.6 Timing Requirements - Data Transmission

VDD = 1.8 ± 5%, TA = 25°C, CL = 100 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(SCL) Serial clock frequency 100
400		 kHz
kHz
t(BUF) Bus free time between stop and start condition SCL = 100 kHz
SCL = 400 kHz		 4.7
1.3		 µs
µs
t(SP) Tolerable spike width on bus SCL = 100 kHz
SCL = 400 kHz		 50 ns
tLOW SCL low time SCL = 100 kHz
SCL = 400 kHz		 4.7
1.3		 µs
µs
tHIGH SCL high time SCL = 100 kHz
SCL = 400 kHz		 4.0
600		 µs
ns
tS(DAT) SDA → SCL setup time SCL = 100 kHz
SCL = 400 kHz		 250
100		 ns
ns
tS(STA) Start condition setup time SCL = 100 kHz
SCL = 400 kHz		 4.7
600		 µs
ns
tS(STO) Stop condition setup time SCL = 100 kHz
SCL = 400 kHz		 4.0
600		 µs
ns
tH(DAT) SDA → SCL hold time SCL = 100 kHz
SCL = 400 kHz		 0
0		 3.45
0.9		 µs
µs
tH(STA) Start condition hold time SCL = 100 kHz
SCL = 400 kHz		 4.0
600		 µs
ns
tr(SCL) Rise time of SCL signal SCL = 100 kHz
SCL = 400 kHz		 1000
300		 ns
ns
tf(SCL) Fall time of SCL signal SCL = 100 kHz
SCL = 400 kHz		 300
300		 ns
ns
tr(SDA) Rise time of SDA signal SCL = 100 kHz
SCL = 400 kHz		 1000
300		 ns
ns
tf(SDA) Fall time of SDA signal SCL = 100 kHz
SCL = 400 kHz		 300
300		 ns
ns

7.7 Typical Characteristics

TPS68470 Eff-Buck-Graph.gif
Figure 1. Buck Efficiency vs. Output Current
TPS68470 Eff-Boost-Graph.gif
Figure 2. Boost Efficiency vs. Output Current