7.3.1 Mode Selection

The MODE pin allows mode selection between forced PWM Mode and Power Save Mode for both converters. Connecting this pin to GND enables the automatic PWM and Power Save Mode operation. The converters operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range.

Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the Power Save Mode during light loads. For additional flexibility, switch from Power Save Mode to forced PWM mode during operation ehich allows efficient power management by adjusting the operation of the converter to the specific system requirements.

7.3.2 Enable

The device has a separate enable pin for each of the DC-DC converters and for each of the LDO to start up independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 are set to high, the corresponding converter starts up with soft start as previously described.

Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the Electrical Characteristics table. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internal control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 350-Ω resistors, actively discharging the output capacitor. For proper operation the enable pins must be terminated and must not be left unconnected.

7.3.3 Reset

The TPS65053-Q1 device contains circuitry that can generate a reset pulse for a processor with a 100-ms delay time. The input voltage at a comparator is sensed at an input called THRESHOLD. When the voltage exceeds the 1-V threshold, the output goes high after a 100-ms delay time. This circuitry is functional as soon as the supply voltage at V_CC exceeds the undervoltage lockout threshold. The RESET circuitry is active even if all DC-DC converters and LDOs are disabled.

Figure 6. RESET Pulse Circuit

7.3.4 Short-Circuit Protection

All outputs are short circuit protected with a maximum output current as defined in the Electrical Characteristics table.

7.3.5 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds 150°C (typical) for the DC-DC converters, the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC-DC converters will disable both converters simultaneously.

The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore an LDO that can be used to power an external voltage will never heat up the chip high enough to turn off the DC-DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs will turn off simultaneously.

7.4.1 Power Save Mode

The Power Save Mode is enabled with the MODE pin set to low. If the load current decreases, the converters enter Power Save Mode operation automatically. During Power Save Mode the converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

To optimize the converter efficiency at light load the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold can be calculated according to Equation 1 and Equation 2.

Equation 1.

where

• I_{PFM_enter} is the average output current threshold to enter PFM mode.

Equation 2.

where

• I_{PFM_leave} is the average output current threshold to leave PFM mode.

During the Power Save Mode the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp) of V_OUTnominal +1%, the P-channel switch will turn on and the converter effectively delivers a constant current as defined above. If the load is below the delivered current then the output voltage will rise until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load current is greater than the delivered current then the output voltage will fall until it crosses the skip comparator low (Skip Comp Low) threshold set to 1% below nominal V_OUT, whereupon Power Save Mode is exited and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 μA per converter and the switching frequency to a minimum thereby achieving the highest converter efficiency. The PFM mode operates with very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values will make the output ripple tend to zero.

The Power Save Mode can be disabled by driving the MODE pin high. Both converters will operate in fixed PWM mode. Power Save Mode Enable/Disable applies to both converters.

7.4.1.1 Dynamic Voltage Positioning

This feature reduces the voltage undershoot and overshoot at load steps from light to heavy load and vice versa. It is activated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom for both the voltage drop at a load step increase and the voltage increase at a load throw-off which improves load transient behavior.

At light loads, in which the converters operate in PFM Mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage will drop until it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch.

Figure 7. Dynamic Voltage Positioning

7.4.1.2 Soft Start

The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 8.

Figure 8. Soft Start

7.4.1.3 100% Duty-Cycle Low Dropout Operation

The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range; essentially the minimum input voltage to maintain regulation depends on the load current and output voltage and can be calculated as shown in Equation 3.

Equation 3.

where

• I_OUTmax = maximum output current plus inductor ripple current
• RDSon_max = maximum P-channel switch r_DS(on)
• R_L = DC resistance of the inductor
• V_OUTmax = nominal output voltage plus maximum output voltage tolerance

With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency.

In Power Save Mode the converter only operates when the output voltage trips below its nominal output voltage. It ramps up the output voltage with several pulses and goes again into Power Save Mode when the output voltage exceeds the nominal output voltage.