ZHCS206A June   2011  – January 2017 TPS65053-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Function
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mode Selection
      2. 7.3.2 Enable
      3. 7.3.3 Reset
      4. 7.3.4 Short-Circuit Protection
      5. 7.3.5 Thermal Shutdown
        1. 7.3.5.1 Low Dropout Voltage Regulators
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode
        1. 7.4.1.1 Dynamic Voltage Positioning
        2. 7.4.1.2 Soft Start
        3. 7.4.1.3 100% Duty-Cycle Low Dropout Operation
        4. 7.4.1.4 Undervoltage Lockout
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting
        2. 8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.2.1 Inductor Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Input Capacitor Selection
        3. 8.2.2.3 Low Dropout Voltage Regulators (LDOs)
          1. 8.2.2.3.1 Input Capacitor and Output Capacitor Selection for the LDOs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage All pins except AGND, PGND, and EN_LDO1 pins with respect to AGND –0.3 7 V
EN_LDO1 pin with respect to AGND –0.3 VCC + 0.5
VO Output voltage for LDO1, LDO2 and LDO3 –0.3 4 V
II Current VINDCDC1/2, L1, PGND1, L2, PGND2 1800 mA
All other pins 1000
TA Operating free-air temperature –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 All pins ±500
Corner pins (1, 6, 7, 12, 13, 18, 19, and 24) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VINDCDC1/2 Input voltage for step-down converters 2.5 6 V
VINLDO1, VINLDO2/3 Input voltage range for LDOs 1.5 6.5 V
VDCDC1 Output voltage range for externally adjustable VDCDC1 step-down converter 0.6 VINDCDC1 V
VDCDC2 Output voltage range for externally adjustable VDCDC2 step-down converter 0.6 VINDCDC2 V
VLDO1-2 Output voltage range for externally adjustable LDO1 and LDO2 1 3.6 V
VLDO3 Output voltage for LDO3 1.3 V
IOUTDCDC1 Output current at L1 1000 mA
IOUTDCDC2 Output current at L2 600 mA
ILDO1 Output current at VLDO1 400 mA
ILDO2,3 Output current at VLDO2 and VLDO3 200 mA
CINDCDC1/2 Input capacitor at VINDCDC1/2(1) 22 μF
CVCC Input capacitor at VCC (1) 1 μF
Cin1-2 Input capacitor at VINLDO1, VINLDO2/3 (1) 2.2 μF
COUTDCDC1 Output capacitor at VDCDC1(1) 10 22 μF
COUTDCDC2 Output capacitor at VDCDC2(1) 10 22 μF
COUT1 Output capacitor at VLDO1 (1) 4.7 μF
COUT2-3 Output capacitor at VLDO2-3 (1) 2.2 μF
L1 Inductor at L1(1) 1.5 2.2 μH
L2 Inductor at L2(1) 1.5 2.2 μH
RCC Resistor from battery voltage to VCC used for filtering(2) 1 10 Ω
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
(1) See the Application and Implementation section of this data sheet for more details.
(2) Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly.

6.4 Thermal Information

THERMAL METRIC(1) TPS65053-Q1 UNIT
RGE (VQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 31.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23.7 °C/W
RθJB Junction-to-board thermal resistance 8.0 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 8.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to +85°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VCC Input voltage range 2.5 6 V
IQ Operating quiescent current
Total current into VCC, VINDCDC1/2, VINLDO1, VINLDO2/3		 One converter, IOUT = 0 mA. PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN; EN_LDO1= EN_LDO2 = EN_LDO3 = GND 30 μA
One converter, IOUT = 0 mA. PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN; EN_LDO1= EN_LDO2 = EN_LDO3 = GND, TA = 25°C 20
Two converters, IOUT = 0 mA, PFM mode enabled (Mode = 0) device not switching, EN_DCDC1 = VIN AND EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND		 40
Two converters, IOUT = 0 mA, PFM mode enabled (Mode = 0) device not switching, EN_DCDC1 = VIN AND EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C		 32
One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN; EN_LDO1 = EN_LDO2 = EN_LDO3 = VIN 210
One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN; EN_LDO1 = EN_LDO2 = EN_LDO3 = VIN, TA = 25°C 145
IQ Operating quiescent current into VCC One converter, IOUT = 0 mA, Switching with no load (Mode = VIN), PWM operation, EN_DCDC1 = VIN OR EN_DCDC2 = VIN; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C 0.85 mA
Two converters, IOUT = 0 mA, Switching with no load (Mode = VIN), PWM operation, EN_DCDC1 = VIN AND EN_DCDC2 = VIN; EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C 1.25 mA
I(SD) Shutdown current EN_DCDC1 = EN_DCDC2 = GND, EN_LDO1 = EN_LDO2 = EN_LDO3 = GND 12 μA
EN_DCDC1 = EN_DCDC2 = GND, EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C 9
UVLO Undervoltage lockout threshold for DC-DC converters and LDOs Voltage at VCC 2 V
Voltage at VCC, TA = 25°C 1.8
EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE
VIH High-level input voltage MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 1.2 VCC V
VIL Low-level input voltage MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 0 0.4 V
IIN Input bias current MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE = GND or VIN, TA = 25°C 0.01 1 μA
POWER SWITCH
rDS(on) P-channel MOSFET on resistance, DCDC1, DCDC2 VINDCDC1/2 = 3.6 V 630 mΩ
VINDCDC1/2 = 3.6 V, TA = 25°C 280
VINDCDC1/2 = 2.5 V, TA = 25°C 400
ILD_PMOS P-channel leakage current V(DS) = 6 V 1 μA
rDS(on) N-channel MOSFET on resistance, DCDC1, DCDC2 VINDCDC1/2 = 3.6 V 450 mΩ
VINDCDC1/2 = 3.6 V, TA = 25°C 220
VINDCDC1/2 = 2.5 V, TA = 25°C 320
ILK_NMOS N-channel leakage current V(DS) = 6 V 10 μA
V(DS) = 6 V, TA = 25°C 7
I(LIMF) Forward current limit PMOS (high side) and NMOS (low side) DCDC1, 2.5 V ≤ VIN ≤ 6 V 1.1 1.8 A
DCDC1, 2.5 V ≤ VIN ≤ 6 V, TA = 25°C 1.4
DCDC2, 2.5 V ≤ VIN ≤ 6 V 0.85 1.15
DCDC2, 2.5 V ≤ VIN ≤ 6 V, TA = 25°C 1
TSD,DCDC Thermal shutdown Increasing junction temperature, TA = 25°C 150 °C
TSDhys,DCDC Thermal shutdown hysteresis Decreasing junction temperature below TSD,DCDC for resuming normal operation, TA = 25°C 20 °C
OSCILLATOR
fSW Oscillator frequency 2.025 2.475 MHz
TA = 25°C 2.25
OUTPUT
VOUT Output voltage range 0.6 VIN V
Vref Reference voltage TA = 25°C 600 mV
VOUT DC output voltage accuracy VIN = 2.5 V to 6 V, Mode = GND, PFM operation,
0 mA < IOUT < IOUTmax		 -2% 0 2%
VIN = 2.5 V to 6 V, Mode = VIN, PWM operation,
0 mA < IOUT < IOUTmax		 –1% 0 1%
ΔVOUT Power save mode ripple voltage(2) IOUT = 1 mA, Mode = GND, VO = 1.3 V, Bandwidth = 20 MHz,
TA = 25°C		 25 mVPP
tStart Start-up time Time from active EN to start switching, TA = 25°C 170 μs
tRamp VOUT ramp up time Time to ramp from 5% to 95% of VOUT, TA = 25°C 750 μs
RESET delay time Input voltage at threshold pin rising 80 120 ms
Input voltage at threshold pin rising, TA = 25°C 100
VOL RESET output low voltage IOL = 1 mA, Vth < 1 V 0.2 V
RESET sink current TA = 25°C 1 mA
RESET output leakage current Vth > 1 V, TA = 25°C 10 nA
Vth Threshold voltage Falling voltage 0.98 1.02 V
Falling voltage, TA = 25°C 1
VLDO1, VLDO2, VLDO3 LOW DROPOUT REGULATORS
VINLDO Input voltage range for LDO1, LDO2, LDO3 1.5 6.5 V
VLDO1 LDO1 output voltage range 1 3.6 V
VLDO2 LDO2 output voltage range 1 3.6 V
VLDO3 LDO3 output voltage TA = 25°C 1.3 V
V(FB) Feedback voltage for FB_LDO1, FB_LDO2 TA = 25°C 1 V
IO Maximum output current for LDO1 400 mA
Maximum output current for LDO2, LDO3 200 mA
I(SC) LDO1 short-circuit current limit VLDO1 = GND 850 mA
LDO2 and LDO3 short-circuit current limit VLDO2 = GND, VLDO3 = GND 420 mA
Dropout voltage at LDO1 IO = 400 mA, VINLDO1 = 1.8 V 280 mV
Dropout voltage at LDO2, LDO3 IO = 200 mA, VINLDO2/3 = 1.8 V 280 mV
Output voltage accuracy for LDO1, LDO2, LDO3(1) IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2, LDO3 VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA –1% 1%
Load regulation for LDO1, LDO2, LDO3 IO = 0 mA to 400 mA for LDO1, IO = 0 mA to 200 mA for LDO2, LDO3 –1% 1%
Regulation time for LDO1, LDO2, LDO3 Load change from 10% to 90%, TA = 25°C 25 μs
R(DIS) Internal discharge resistor at VLDO1, VLDO2, VLDO3 Active when LDO is disabled, TA = 25°C 350 Ω
TSD,LDO Thermal shutdown Increasing junction temperature 140 °C
TSDhys,LDO Thermal shutdown hysteresis Decreasing junction temperature below TSD,LDO for resuming normal operation 20 °C
(1) Output voltage specification does not include tolerance of external voltage programming resistors.
(2) In Power Save Mode, operation is typically entered at IPSM = VIN / 32 Ω.

6.6 Typical Characteristics

TPS65053-Q1 eff1_v_vo_lvs754.gif
VDCDC1 = 2.85 V VINDCDC1/2 = 3.4, 3.8, 4.2, and 5 V
Figure 1. Efficiency (η) of DCDC1 in PWM/PFM Mode
TPS65053-Q1 eff3_v_vo_lvs754.gif
VDCDC2 = 1.8 V VINDCDC1/2 = 3.4, 3.8, 4.2, and 5
Figure 3. Efficiency (η) of DCDC2 in PWM/PFM Mode
TPS65053-Q1 pssr_v_f_lvs754.gif Figure 5. LDO1 Power-Supply Rejection Ratio
TPS65053-Q1 eff2_v_vo_lvs754.gif
VDCDC1 = 2.85 V VINDCDC1/2 = 3.4, 3.8, 4.2, and 5 V
Figure 2. Efficiency (η) of DCDC1 in PWM Mode
TPS65053-Q1 eff4_v_vo_lvs754.gif
VDCDC2 = 1.8 V VINDCDC1/2 = 3.4, 3.8, 4.2, and 5 V
Figure 4. Efficiency (η) of DCDC2 in PWM Mode