ZHCS206A June   2011  – January 2017 TPS65053-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Function
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mode Selection
      2. 7.3.2 Enable
      3. 7.3.3 Reset
      4. 7.3.4 Short-Circuit Protection
      5. 7.3.5 Thermal Shutdown
        1. 7.3.5.1 Low Dropout Voltage Regulators
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode
        1. 7.4.1.1 Dynamic Voltage Positioning
        2. 7.4.1.2 Soft Start
        3. 7.4.1.3 100% Duty-Cycle Low Dropout Operation
        4. 7.4.1.4 Undervoltage Lockout
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting
        2. 8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.2.1 Inductor Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Input Capacitor Selection
        3. 8.2.2.3 Low Dropout Voltage Regulators (LDOs)
          1. 8.2.2.3.1 Input Capacitor and Output Capacitor Selection for the LDOs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Function

RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 24 I Analog GND, connect to PGND and thermal pad
EN_DCDC1 20 I Enable Input for converter 1, active high
EN_DCDC2 21 I Enable Input for converter 2, active high
EN_LDO1 22 I Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2 11 I Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3 12 I Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
FB_DCDC1 19 I Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect external resistor divider between VOUT1, this pin and GND.
FB_DCDC2 13 I Input to adjust output voltage of converter 2 between 0.6 V and VIN. Connect external resistor divider between VOUT2, this pin and GND.
FB_LDO1 4 I Feedback input for the external voltage divider.
FB_LDO2 6 I Feedback input for the external voltage divider.
L1 17 O Switch pin of converter 1. Connected to Inductor
L2 15 O Switch Pin of converter 2. Connected to Inductor.
MODE 23 I Select between Power Save Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Save Mode, PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then the device operates in Power Save Mode.
PGND1 18 I GND for converter 1
PGND2 14 I GND for converter 2
RESET 10 O Open drain active low reset output, 100-ms reset delay time.
THRESHOLD 5 I Reset input
VCC 1 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same voltage supply as VINDCDC1/2.
VINDCDC1/2 16 I Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as VCC.
VINLDO1 2 I Input voltage for LDO1
VINLDO2/3 8 I Input voltage for LDO2 and LDO3
VLDO1 3 O Output voltage of LDO1
VLDO2 7 O Output voltage of LDO2
VLDO3 9 O Output voltage of LDO3
Thermal Pad — Connect to GND