SLVS294F September 2000 – August 2015 TPS62000 , TPS62002 , TPS62003 , TPS62004 , TPS62005 , TPS62006 , TPS62007 , TPS62008
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 8 | I | Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 1 μA. |
FB | 5 | I | Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is connected to FB. The internal voltage divider is disabled for the adjustable version. |
FC | 2 | — | Supply bypass pin. A 0.1-μF coupling capacitor should be connected as close as possible to this pin for good high frequency input voltage supply filtering. |
GND | 3 | — | Ground |
ILIM | 6 | I | Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin to VIN to set the current limit to typically 1200 mA. |
L | 9 | I/O | Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS. |
PG | 4 | O | Power good comparator output. This is an open-drain output. A pull-up resistor should be connected between PG and VOUT. The output goes active high when the output voltage is greater than 92% of the nominal value. |
PGND | 10 | — | Power ground. Connect all power grounds to PGND. |
SYNC | 7 | I | Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level: SYNC = High: Low-noise mode enabled, fixed frequency PWM operation is forced SYNC = Low (GND): Power save mode enabled, PFM/PWM mode enabled |
VIN | 1 | I | Supply voltage input |