SLVS273A February   2000  – November 2015 TPS60140 , TPS60141

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout
      2. 9.3.2 Low-Battery Detector (TPS60140 Only)
      3. 9.3.3 Power-Good Detector (TPS60141)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-Up Procedure and Shutdown
      2. 9.4.2 Short-Circuit Protection
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Capacitor Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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7 Pin Configuration and Functions

PWP Package (TPS60140)
20 Pin-HTSSOP
Top View
TPS60140 TPS60141 pin_01_slvs273.gif
PWP Package (TPS60141)
20 Pin-HTSSOP
Top View
TPS60140 TPS60141 pin_02_slvs273.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
C1+ 6 — Positive terminal of the flying capacitor C1
C1− 8 — Negative terminal of the flying capacitor C1
C2+ 15 — Positive terminal of the flying capacitor C2
C2− 13 — Negative terminal of the flying capacitor C2
ENABLE 3 I ENABLE input. Connect ENABLE to IN for normal operation. When ENABLE is a logic low, the device turns off and the supply current decreases to 0.05 µA. The output is disconnected from the input when the device is placed in shutdown.
FB 4 I Feedback input. Connect FB to OUT as close to the load as possible to achieve best regulation. A resistive divider is on the chip to match the output voltage to the internal reference voltage of 1.21 V.
GND 1, 2, 19, 20 — Ground. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
IN 7,14 I Supply input. Bypass IN to PGND with capacitor CIN. Connect both IN terminals through a short trace.
LBO/PG 17 O Low battery detector output (TPS60140) or power good output (TPS60141). Open-drain output of the low-battery indicator or power-good comparator. It can sink 1 mA. TI recommends a 100-kΩ to 1-MΩ pullup. Leave the terminal unconnected if the low-battery or power-good detector function is not used.
LBI/NC 18 I Low battery detector input (TPS60140 only). The voltage applied to this terminal is compared to the internal 1.21-V reference voltage. Connect the terminal to ground if the low-battery comparator is not used. On the TPS60141, this terminal is not connected to the chip and should remain unconnected.
NC 16 — Not connected
OUT 5 O Regulated 5-V power output. Bypass OUT to PGND with the output filter capacitor COUT.
PGND 9−12 — Power ground. The charge-pump current flows through this terminal. Connect all PGND terminals together.