ZHCSL72B October   2016  – July 2021 TPS57114C-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
        1. 7.3.3.1 Error Amplifier
      4. 7.3.4 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using The RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Slow-Start Capacitor
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Output-Voltage And Feedback-Resistor Selection
        8. 8.2.2.8 Compensation
        9. 8.2.2.9 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.4.4 Sequencing

One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. Implementation of the sequential method can be by using an open-drain or open-collector output of the power-on-reset pin of another device. Figure 7-3 shows the sequential method. Coupling power-good to the EN pin on the TPS57114C-Q1 device enables the second power supply once the primary supply reaches regulation.

One can accomplish ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, double the pullup current source in Equation 4. Figure 7-5 illustrates the ratiometric method.

GUID-EFB0AC93-641C-4A9D-A9AA-5160620B5B7C-low.gif
 
 
 
 
 
Figure 7-3 Sequential Start-Up Sequence
GUID-D85096DA-0BD9-4FAB-8493-8A59008134E9-low.gifFigure 7-5 Schematic for Ratiometric Start-Up Sequence
GUID-C25D3B3B-2CA6-467A-852A-8847FFE98DBE-low.gifFigure 7-4 Sequential Start-Up Using EN and PWRGD
GUID-F0C13747-5892-4BEB-B253-AF50C55649B2-low.gif
 
 
Figure 7-6 Ratiometric Start-Up with VO(1) Leading VO(2)

One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 7-7 to the output of the power supply that requires tracking, or to another voltage reference source. Using Equation 5 and Equation 6 allows calculation of the tracking resistors to initiate VO(2) slightly before, after, or at the same time as VO(1). VO(1) – VO(2) is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR-to-VSENSE offset (V(ssoffset)) in the slow-start circuit and the offset created by the pullup current source (I(SS/TR)) and tracking resistors, the equations include V(ssoffset) and I(SS/TR) as variables. The requirement to pull the SS/TR pin below 60 mV before starting after an EN, UVLO, or thermal shutdown fault necessitates careful selection of the tracking resistors to ensure the device can restart after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 7 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(ssoffset) becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference, as shown in Figure 7-6.

Equation 5. GUID-26FB2F81-610B-4F3A-9EE3-C396C8A4F636-low.gif
Equation 6. GUID-98EEB7EC-46FB-486D-A7E8-5823A2776528-low.gif
Equation 7. GUID-81CB4F54-450D-4A29-AAAA-82A38FDE2A98-low.gif
GUID-E27DFBA7-F725-4C20-B4F7-AD1D7A3823F6-low.gifFigure 7-7 Ratiometric and Simultaneous Start-Up Sequence
GUID-96D16990-5F6D-4A3E-91B4-28DBEA280351-low.gifFigure 7-8 Ratiometric Start-Up Using Coupled SS/TR Pins