ZHCSAH1B November   2012  – April 2019 TPS53819A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive On-Time Control
      3. 7.3.3  Zero Crossing Detection
      4. 7.3.4  Output Discharge Control
      5. 7.3.5  Low-Side Driver
      6. 7.3.6  High-Side Driver
      7. 7.3.7  Power Good
      8. 7.3.8  Current Sense and Overcurrent Protection
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Out-of-Bound Protection
      11. 7.3.11 UVLO Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light-Load Condition in Auto-Skip Operation (Eco-mode)
      2. 7.4.2 Forced Continuous Conduction Mode
      3. 7.4.3 D-CAP2™ Mode
    5. 7.5 Programming
      1. 7.5.1 PMBus General Descriptions
      2. 7.5.2 PMBus Slave Address Selection
      3. 7.5.3 PMBus Address Selection
      4. 7.5.4 Supported Formats
        1. 7.5.4.1 Direct Format: Write
        2. 7.5.4.2 Combined Format: Read
        3. 7.5.4.3 Stop-Separated Reads
      5. 7.5.5 Supported PMBus Commands
      6. 7.5.6 Unsupported PMBus Commands
    6. 7.6 Register Maps
      1. 7.6.1  OPERATION [01h] (R/W Byte)
      2. 7.6.2  ON_OFF_CONFIG [02h] (R/W Byte)
      3. 7.6.3  WRITE_PROTECT [10h] (R/W Byte)
      4. 7.6.4  CLEAR_FAULTS [03h] (Send Byte)
      5. 7.6.5  STORE_DEFAULT_ALL [11h] (Send Byte)
      6. 7.6.6  RESTORE_DEFAULT_ALL [12h] (Send Byte)
      7. 7.6.7  STATUS_WORD [79h] (Read Word)
      8. 7.6.8  CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)
      9. 7.6.9  DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)
      10. 7.6.10 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)
      11. 7.6.11 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)
      12. 7.6.12 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)
      13. 7.6.13 Output Voltage Fine Adjustment Soft Slew Rate
      14. 7.6.14 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)
      15. 7.6.15 Output Voltage Margin Adjustment Soft-Slew Rate
      16. 7.6.16 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Inductor (L1)
        4. 8.2.2.4  Output Capacitors (C10, C11, C12, C13, C14)
        5. 8.2.2.5  Input Capacitors (C1, C2, C3, C4, C5)
        6. 8.2.2.6  MOSFET (Q1, Q2)
        7. 8.2.2.7  VREG Bypass Capacitor (C18)
        8. 8.2.2.8  VDD Bypass Capacitor (C19)
        9. 8.2.2.9  VBST Capacitor (C7)
        10. 8.2.2.10 Snubber (C8 and R9)
        11. 8.2.2.11 Feedback Resistance, RFBH and RFBL (R17 and R18)
        12. 8.2.2.12 Overcurrent Limit (OCL) Setting Resistance (R10)
        13. 8.2.2.13 PMBus Device Address (R3 and R4)
        14. 8.2.2.14 PGOOD Pullup Resistor (R2)
        15. 8.2.2.15 SCL and SDA Pulldown Resistors (R14 and R15)
        16. 8.2.2.16 PMBus Pullup Resistors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.9 DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)

Custom register 1 provides software control over key timing parameters of the controller: Power-on delay (POD) time and power-good delay (PGD) time. The details of each setting are listed in Table 9.

Table 9. DELAY_CONTROL (MFR_SPECIFIC_01) Settings

COMMAND DEFINITION DESCRIPTION NVM
DELAY_CONTROL<7> — not supported and don’t care —
DELAY_CONTROL<6> — not supported and don’t care —
DELAY_CONTROL<5:3> PGD<2:0> 000: 256 µs
001: 512 µs
010: 1.024 ms(1)
011: 2.048 ms
100: 4.096 ms
101: 8.192 ms
110: 16.384 ms
111: 131.072 ms		 Yes
DELAY_CONTROL<2:0> POD<2:0> 000: 356 µs
001: 612 µs
010: 1.124 ms(1)
011: 2.148 ms
100: 4.196 ms
101: 8.292 ms
110: 16.484 ms
111: 32.868 ms		 Yes
(1) TI default