ZHCSHF4J May   2004  – January 2018 TPS51116

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1. 3.1 典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Dissipation Ratings
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDDQ SMPS, Light Load Condition
      2. 7.3.2  Low-Side Driver
      3. 7.3.3  High-Side Driver
      4. 7.3.4  Current Sensing Scheme
      5. 7.3.5  PWM Frequency and Adaptive On-Time Control
      6. 7.3.6  VDDQ Output Voltage Selection
      7. 7.3.7  VTT Linear Regulator and VTTREF
      8. 7.3.8  Controling Outputs Using the S3 and S5 Pins
      9. 7.3.9  Soft-Start Function and Powergood Status
      10. 7.3.10 VDDQ and VTT Discharge Control
      11. 7.3.11 Current Protection for VDDQ
      12. 7.3.12 Current Protection for VTT
      13. 7.3.13 Overvoltage and Undervoltage Protection for VDDQ
      14. 7.3.14 Undervoltage Lockout (UVLO) Protection, V5IN (PWP), V5FILT (RGE)
      15. 7.3.15 Input Capacitor, V5IN (PWP), V5FILT (RGE)
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDDQ SMPS, Dual PWM Operation Modes
      2. 7.4.2 Current Mode Operation
      3. 7.4.3 D-CAP™ Mode Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 DDR3 Application With Current Mode
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pin Connections
        2. 8.2.2.2 Choose the inductor
        3. 8.2.2.3 Choose rectifying (low-side) MOSFET
        4. 8.2.2.4 Choose output capacitance
        5. 8.2.2.5 Determine f0 and calculate RC
        6. 8.2.2.6 Calculate CC2
        7. 8.2.2.7 Calculate CC.
        8. 8.2.2.8 Determine the value of R1 and R2.
      3. 8.2.3 Application Curves
    3. 8.3 DDR3 Application With D−CAP™ Mode
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Pin Connections
        2. 8.3.2.2 Choose the Components
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RGE|24
  • PWP|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.7 VTT Linear Regulator and VTTREF

The TPS51116 device integrates high performance low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. It is recommended to attach two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-μF ceramic capacitor for stable operation.

When VTT is not required in the design, following treatment is strongly recommended.

  • Connect VLDOIN to VDDQSNS.
  • Tie VTTSNS to VTT, and remove capacitors from VTT to float.
  • Connect VTTGND and MODE to GND (Non-tracking discharge mode as shown in Table 3)
  • Maintain a 0.033-µF capacitor connected at VTTREF.
  • Pull down S3 to GND with 1 kΩ of resistance.

A typical circuit for this application is shown in Figure 34

TPS51116 v12044_lus609.gifFigure 34. Application Circuit When VTT Is Not Required